Ring Oscillator DCO Dithering for Linear Frequency Control
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Solution Overview
Problem
Existing ring oscillators used as digitally controlled oscillators (DCOs) in phase-locked loops (PLLs) face non-linearity issues due to the use of capacitive or resistive DACs to ensure constant delay, leading to inefficiencies and design complexity.
Innovation Solution
A ring oscillator design with alternating groups of inverter stages, where one group has controllable delays and the other has static delays, allowing frequency control through frequency control signals, and utilizing a dithering mechanism with least significant bits to achieve high-speed frequency changes within one cycle, reducing non-linearity and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a capacitive digital to analog converter (CDAC) or a resistive DAC (RDAC) is used to ensure constant delay through each stage of the ring oscillator, then delay uniformity is improved, but device complexity and area increase
Solution Approach 1:
The patent extracts and removes the complex CDAC/RDAC components from the ring oscillator design. Instead of using these dedicated converters to control delay, the invention uses direct digital control signals applied to individual inverter stages, eliminating the need for separate capacitive or resistive conversion circuits while maintaining delay uniformity through alternative means.
Solution Approach 2:
The patent replaces the mechanical/electrical conversion system (CDAC/RDAC) with a direct digital control approach. Frequency control signals in digital form are applied directly to control the delay of inverter stages without requiring analog conversion through capacitive or resistive networks, thereby reducing device complexity while maintaining functionality.
2Stability of the object's composition
If a capacitive digital to analog converter (CDAC) or a resistive DAC (RDAC) is used to ensure constant delay through each stage of the ring oscillator, then delay uniformity is improved, but area increases
Solution Approach 1:
The patent removes the area-consuming CDAC/RDAC components from the ring oscillator structure. By eliminating these dedicated converter circuits and using direct digital control signals applied to inverter stages, the invention achieves delay uniformity without occupying additional silicon real estate.
3Adaptability or versatility
If frequency control signals are applied to control delays through inverter stages, then frequency control capability is improved, but non-linearity issues arise
Solution Approach 1:
The patent segments the ring oscillator into two distinct groups of inverter stages: a first group with controllable delay for frequency tuning and a second group with static delay for reference. This segmentation allows independent optimization of each group's function, enabling frequency control capability while the static reference group provides a stable baseline that helps maintain linearity in the overall frequency response.
Solution Approach 2:
The patent applies different delay characteristics to different parts of the oscillator: the first group of inverter stages has controllable delay for frequency adjustment, while the second group has static delay for stability. This local differentiation of delay properties allows frequency control capability in the first group while the second group maintains linearity by providing a consistent reference point.
4Measurement precision
If dithering is implemented using least significant bits of the frequency control word, then resolution is improved, but processing complexity increases
Solution Approach 1:
The patent implements dithering by periodically adding 1 to the most significant bits of the frequency control word based on an accumulator of least significant bits. This periodic action, triggered when the accumulator reaches a predetermined value, achieves high-resolution frequency control through a simple counter-based mechanism rather than complex processing logic.
Data Source
AI summary
A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.