Ring Oscillator Sampling Circuit for Faster True Random Numbers
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Solution Overview
Problem
Existing random number generators face challenges in generating true random numbers efficiently due to high jitter in oscillation signals, which affects the speed and reliability of the random number generation process.
Innovation Solution
A random number generating circuit is designed with a ring oscillator and a sampling circuit that includes multiple delay elements to generate oscillation and sampling signals, allowing for the determination of a target sampling point with minimal jitter, thereby improving the speed and efficiency of random number generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ring oscillator is used to generate oscillation signals for random number generation, then true random numbers can be generated based on physical jitter phenomena, but the high jitter in the oscillation signal causes delays and reduces the speed of random number generation
Solution Approach 1:
The patent divides the oscillation signal processing into multiple segments by using several delay elements (first delay element, second delay element, third delay element) that sample the oscillation signal at different time points. This segmentation allows the system to process multiple samples in parallel and select the most suitable sample, thereby reducing the impact of jitter on generation speed while maintaining reliability.
Solution Approach 2:
The patent dynamically selects the optimal sampling point from multiple delayed versions of the oscillation signal based on actual jitter conditions. The sampling circuit adjusts which delayed signal is used for random number generation, allowing the system to adapt to varying jitter patterns and maintain high-speed operation without sacrificing the reliability provided by physical jitter.
2Reliability
If multiple delay elements are added to sample the oscillation signal at different time points, then the impact of jitter can be reduced, but the device complexity increases
Solution Approach 1:
The patent implements a nested structure where delay elements are arranged in a hierarchical manner, with each delay element processing the output of the previous one. The delay elements form a cascade where the second delay element processes the signal delayed by the first, and the third processes the signal from the second. This nested arrangement manages complexity by organizing multiple delay elements in a systematic, modular fashion rather than requiring independent complex circuitry for each sampling point.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively reduces jitter-based delays, enabling faster generation of random numbers with improved performance by independently configuring the sampling circuit to manage required jitter, thus enhancing the speed and reliability of the random number generation process.
Implementation Method 1
A transition time point of a signal output by the ring oscillator may be randomly changed according to a Gaussian distribution, and such a Gaussian distribution range may be referred to as jitter
Implementation Method 2
a second delay element chain including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements
Data Source
AI summary
A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.