Ring Oscillator Test Circuit for GaN Reliability
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Solution Overview
Problem
Current semiconductor device reliability testing assumes a single dominant failure mechanism, leading to misleading assessments when multiple mechanisms exist, and is inadequate for testing high voltage or high power devices like GaN semiconductor devices.
Innovation Solution
A ring oscillator test circuit with an odd number of stages, where each stage consists of a load and drive transistor connected in series, allowing independent control of drain and gate voltages to test transistors under various conditions, including High Voltage Gate Bias and High Voltage Reverse Bias, suitable for GaN and other wide band gap semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ring oscillator circuits are used for testing enhancement-mode transistors (such as GaN), then the circuit cannot operate properly because enhancement-mode transistors do not automatically ring in conventional configurations, but modifying the circuit to accommodate these transistors requires a different topology that works for all enhancement-mode devices
Solution Approach 1:
The patent inverts the conventional ring oscillator topology by making the load transistor the active switching element and the drive transistor the passive load element. This inversion allows enhancement-mode transistors to properly ring in the circuit, as the load transistor (connected to V2) actively switches while the drive transistor (connected to V1) serves as the load, enabling proper operation with GaN and other enhancement-mode devices
2Reliability
If power devices are tested by incorporating them into actual circuits with maximum rated drain voltage, then high voltage testing is achieved, but the maximum gate voltage is much smaller making simple ring-oscillator testing irrelevant
Solution Approach 1:
The patent segments the voltage control functions by separating drain voltage control (V1) from gate voltage control (V2). Each voltage source can be independently adjusted to appropriate levels, allowing the drain to be tested at high voltages while the gate operates at appropriate lower voltages, enabling comprehensive power device testing
Solution Approach 2:
The patent makes the circuit dynamically adaptable by allowing independent adjustment of V1 and V2 voltage levels. This dynamic configuration enables the same circuit to be adapted for different testing scenarios including high voltage reverse bias, high voltage gate bias, and normal operating conditions
3Device complexity
If accelerated life tests assume a single dominant failure mechanism, then the test design is simplified, but the reliability assessment becomes misleading when multiple failure mechanisms exist
Solution Approach 1:
The patent creates a universal test circuit that can evaluate multiple failure mechanisms simultaneously by independently controlling drain and gate voltages. The circuit can stress-test for hot carrier injection, time-dependent dielectric breakdown, NBTI, and other failure mechanisms in a single integrated platform, eliminating the need for separate specialized tests
Data Source
AI summary
A ring oscillator test circuit, includes an odd number of stages, where each stage includes a load and drive transistor connected in series at a common node. The common node of each stage is electrically connected to the drive transistor gate of the following stage, and the common node of the last stage is connected to the drive transistor gate of the first stage. A first voltage input connects to the drains of all the load transistors. A second voltage input connects to the gates of all of the load transistors. A reference voltage input connects to the sources of all of the drive transistors. At least one of the common nodes connects to a test output.