RISC-V Register Bank Initialization Without Reset Lines
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Solution Overview
Problem
RISCV processors have a significant area occupation due to the need for parallel initialization of registers, leading to higher costs, power consumption, and signal congestion, which is typically addressed by using individual reset lines for each memory element.
Innovation Solution
The implementation of a register bank with without-reset type memory elements, initialized using a predefined initialization datum generated by an initialization datum generation module, eliminating the need for individual reset lines by integrating initialization into the write mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If individual reset lines are used for each memory element to enable parallel initialization, then the registers can be initialized simultaneously, but the processor area occupation increases significantly
Solution Approach 1:
The patent merges the initialization function into the existing write mode operation. The same write circuitry and control logic are used for both writing data to registers and initializing them, eliminating the need for separate reset lines. A single shared write line carries both data and initialization signals, reducing area occupation while maintaining initialization capability.
Solution Approach 2:
The write mode circuitry is designed to perform multiple functions: normal data writing and register initialization. The control logic can distinguish between these modes and route appropriate signals through the shared write infrastructure, making the system more area-efficient by eliminating dedicated reset lines for each memory element.
2Reliability
If individual reset lines are provided for each memory element, then reliable initialization is achieved, but the number of electrical connections increases causing signal congestion
Solution Approach 1:
Multiple reset functions are merged into a single shared write line. This line carries initialization data to multiple memory elements simultaneously through the existing write distribution network, reducing the number of electrical connections while ensuring reliable initialization of all registers.
Solution Approach 2:
The write circuitry acts as an intermediary that receives initialization commands and distributes them to the appropriate memory elements. This mediator approach allows reliable initialization without requiring direct reset connections to each memory element, thereby reducing electrical connection complexity.
3Productivity
If parallel initialization with individual reset lines is implemented, then all registers are initialized simultaneously, but power consumption increases
Solution Approach 1:
The initialization operation merges with the normal write operation, utilizing the same power-efficient write circuitry and control logic. This eliminates the need for separate high-power reset lines while maintaining the ability to initialize all registers in parallel through the shared write infrastructure.
Data Source
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AI summary
Register bank (50) for an electronic processor (10), comprising a first plurality of registers (60). The register bank (50) has a write datum input (50a) to receive a write datum (D), a write enable input (50b) to receive a write enable signal (WR_EN) and an write address input (50c) to receive a write address signal (WR_ADDR). The register bank (50) is controllable in an initialization mode wherein the register (60) identified by the address present in the write address signal (WR_ADDR) is initialized on the basis of an initialization datum (D_INIT) of predefined type.