RISC-V Floating-Point Exponential Hardware Without Lookup Tables
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Solution Overview
Problem
Conventional processors, particularly those compliant with the RISC-V instruction set architecture, lack specific hardware support for efficiently computing transcendental functions such as the exponential function (e^x), leading to inefficiencies in non-linear arithmetic operations due to the use of memory-inefficient lookup tables and significant error in computation.
Innovation Solution
Implementing hardware support for a custom floating-point exponent function instruction in a RISC-V processor, utilizing a floating-point unit (FPU) with additional control logic to execute the exponential function efficiently, combining RISC-V 'F' extension instructions with custom instructions to perform the computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processors use memory lookup tables to compute transcendental functions, then the computation can be performed, but the memory efficiency is poor and computation speed is slow
Solution Approach 1:
The patent replaces the conventional software-based lookup table approach with a dedicated hardware circuit (exponential function computing circuit) that directly computes e^x using mathematical decomposition and parallel computation, eliminating the need for large memory tables and significantly improving computation speed
Solution Approach 2:
The exponential function computation is segmented into multiple parallel computational paths: integer part handling, fractional part handling, and exponentiation operations, allowing simultaneous computation of different components to improve overall processing efficiency
2Measurement precision
If conventional processors lack specific hardware support for exponential functions, then the processor design remains simple, but the computation accuracy is poor due to significant error
Solution Approach 1:
The patent introduces an intermediary control unit that coordinates between the instruction decoder, operational register, and exponential function computing circuit, ensuring precise control of the computation process and accurate result generation while maintaining modular hardware architecture
Solution Approach 2:
The patent performs preliminary decomposition of the input value into integer and fractional parts before computation, and pre-configures the hardware circuit with necessary computational components (such as shift registers and adders) to ensure accurate exponential function calculation
Data Source
AI summary
A processor including an instruction decoder configured to provide at least floating-point instruction control signals, a floating-point computational data path, a floating-point custom instruction control logic block coupled to the floating-point computational data path, a control and status register coupled to the floating-point computational data path, and the floating-point custom instruction control logic block, a first multiplexor configured to provide either floating-point instruction control signals or custom instruction control signals to the floating-point computational data path based on the state of a select control signal, and a second multiplexor configured to provide either floating-point operands or custom operands to the floating-point computational data path based on the state of the select control signal. The floating-point custom instruction control logic block asserts the select signal while directing the floating-point computational data path to assist it with the execution of a custom instruction. The custom instruction may be a floating-point exponential function.