RNN Hardware Accelerator With Instruction-Level Resource Control
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Solution Overview
Problem
Existing hardware accelerators for neural networks, particularly Recurrent Neural Networks (RNNs), face challenges in high resource utilization, data splicing inefficiencies, data dependency management, and resource conflicts leading to low computational efficiency.
Innovation Solution
A hardware accelerator designed specifically for RNNs, incorporating a customized instruction set including data flow control, general-type and special-type computing instructions, exponential shift, and data transfer instructions, along with optimized memory and register structures to manage data flow and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If universal hardware accelerators are designed to support both CNNs and RNNs, then adaptability is improved, but computing resource utilization deteriorates
Solution Approach 1:
The hardware accelerator is segmented into dedicated RNN computing units separate from general-purpose units. The architecture includes specialized RNN core units that handle recurrent neural network computations independently, allowing optimized resource allocation for RNN workloads without compromising overall system adaptability to other neural network types.
Solution Approach 2:
Different regions of the hardware accelerator are assigned different functional qualities. The RNN computing units are specifically designed with local optimizations for handling sequential data dependencies and recurrent computations, while other regions maintain general-purpose capabilities. This local differentiation enables high utilization for RNNs while preserving versatility.
2Productivity
If data splicing operations are added to handle RNN data flow, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The data splicing function is merged with the existing data transfer and memory management subsystems. By combining splicing operations with standard data handling pathways, the patent avoids creating entirely separate complex data processing pathways, thus improving data processing capability while limiting the increase in overall device complexity.
Solution Approach 2:
An intermediary data buffer structure is introduced between memory and computing units to handle data splicing operations. This buffer acts as a mediator that manages the complexity of data flow manipulation internally, presenting a simplified interface to the rest of the system and reducing the apparent complexity from external perspectives.
3Reliability
If pipeline stopping mechanisms are implemented to manage data dependencies, then data dependency management is improved, but computing resource utilization deteriorates
Solution Approach 1:
The pipeline control mechanism is made dynamic rather than static. The system can adaptively adjust pipeline behavior based on actual data dependency conditions, allowing flexible control that maintains reliability while maximizing resource utilization. The pipeline can dynamically resume or pause based on computed data availability rather than following fixed stopping rules.
Solution Approach 2:
A feedback mechanism is implemented that monitors data dependency status and automatically adjusts pipeline execution accordingly. This feedback loop allows the system to maintain proper data dependency management while optimizing resource utilization by preventing unnecessary pipeline stops and enabling overlapping operations where data dependencies permit.
4Reliability
If software scheduling is used to balance resources, then resource conflict management is improved, but computational efficiency deteriorates
Solution Approach 1:
The patent replaces software-based scheduling mechanisms with hardware-level resource management circuits. This substitution eliminates the need for continuous software intervention in resource allocation, reducing overhead and improving computational efficiency while maintaining reliable resource conflict management through dedicated hardware control logic.
Data Source
AI summary
A hardware accelerator for running an instruction set of a recurrent neural network, a data processing method, a system-level chip, and a medium are provided. The hardware accelerator is configured to process the instruction set. The instruction set includes: a data flow control instruction used for performing data flow control; a general-type computing instruction used for performing general-type computation to implement general-type computation in the recurrent neural network; a special-type computing instruction used for performing special-type computation to implement special-type computation in the recurrent neural network; an exponential shift instruction used for performing exponential shifting to implement data normalization during computation of the recurrent neural network; and a data transfer instruction used for performing data transfer to implement data transfer operations between different registers as well as data transfer operations between registers and memories during computation of the recurrent neural network.