ROIC Substrate Replacement to Eliminate Interconnect Strain

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Solution Overview

Problem

Current electro-optical sensors face challenges in maintaining interconnect integrity between detectors and read-out integrated circuits (ROICs) due to differential thermal expansion, especially with increasing thermal cycle requirements and larger arrays operating in varying temperature environments.

Innovation Solution

The method involves replacing the initial ROIC substrate with a new one that matches the coefficient of thermal expansion (CTE) of the detector substrate, and hybridizing the detector layers to the ROIC layers using interconnects, which can be deposited before or after bonding, to eliminate interconnect strains caused by thermal cycling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the initial ROIC substrate is used with the detector, then the ROIC can be manufactured and assembled, but differential thermal expansion causes interconnect strain during thermal cycling

Engineering Contradiction:
ImproveROIC assembly manufacturingVSAvoidinterconnect integrity during thermal cycling
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the CTE parameter of the ROIC substrate by replacing the initial ROIC substrate with a new substrate having a CTE matched to the detector substrate. This parameter change eliminates differential thermal expansion and interconnect strain during thermal cycling while maintaining manufacturability of the ROIC assembly.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The new CTE-matched ROIC substrate acts as an intermediary between the detector substrate and the ROIC layers. It serves as a thermal expansion mediator that eliminates differential expansion stresses, allowing the ROIC to be manufactured and assembled without compromising interconnect integrity during thermal cycling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If arrays increase in size and operate at lower temperatures, then detection capability improves, but thermal cycle requirements become more difficult to meet

Engineering Contradiction:
Improvedetection capabilityVSAvoidthermal cycle hybrid reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent changes the thermal expansion parameter (CTE) of the ROIC substrate to match the detector substrate. This enables larger arrays to operate at lower temperatures with improved detection capability while eliminating thermal expansion mismatches that would otherwise cause interconnect failure during required thermal cycling.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If more thermal cycles are required, then operational demands increase, but interconnect integrity becomes harder to maintain

Engineering Contradiction:
Improveoperational capacityVSAvoidinterconnect integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the CTE parameter of the ROIC substrate to match the detector substrate, eliminating differential thermal expansion. This allows the system to withstand 10,000 or more thermal cycles required by modern operational demands without compromising interconnect integrity between the detector and ROIC.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly improves thermal cycle hybrid reliability, allowing for virtually unlimited cooldown cycles and reduces stresses between the detector and ROIC, minimizing image artifacts and detector bowing, thereby enhancing the overall hybrid reliability of interconnects.

Implementation Method 1

the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate

Methodology Applied
Scientific EffectCoefficient of thermal expansion (CTE) matching: Thermal Expansion

Data Source

PatentUS20230411427A1Eliminating interconnect strains in microcircuits
Publication Date: 2023.12.21 RAYTHEON CO
  • US20230411427A1 patent drawing
  • US20230411427A1 patent drawing
  • US20230411427A1 patent drawing

AI summary

A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.