ROM Cell Dielectric Programming for Uniform Contact Via Layout

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Solution Overview

Problem

Existing ROM devices/arrays face manufacturing issues due to uneven distribution of contact via structures, leading to inefficiencies in programming and data storage.

Innovation Solution

A memory device with a uniform distribution of contact via structures across the memory array is achieved by replacing some epitaxial structures with dielectric materials, allowing for even formation of contact via structures and interconnects, and programming ROM cells through FEOL and BEOL processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If contact via structures are formed in conventional ROM devices, then data storage is enabled, but uneven distribution of contact via structures occurs leading to manufacturing inefficiencies

Engineering Contradiction:
Improveuniform distribution of contact via structuresVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by forming a dielectric structure in advance within the active region before contact via structures are formed. This pre-positioned dielectric structure serves as a template that guides the subsequent formation of contact via structures, ensuring their uniform distribution across the memory array. The dielectric structure is formed during FEOL processing, allowing contact vias to be uniformly distributed without requiring complex later-stage adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by introducing a dielectric structure at specific locations within the active region, creating localized differences in material composition. This dielectric structure is positioned only in regions where contact via structures need to be formed, providing local control over the distribution pattern. The selective placement of dielectric material enables precise control of contact via formation without affecting the entire device uniformly.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If epitaxial structures are used in ROM cells, then transistor functionality is achieved, but replacing some with dielectric materials adds manufacturing complexity

Engineering Contradiction:
Improveprogramming process simplificationVSAvoidstructure composition
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the dielectric structure to serve multiple functions simultaneously. The dielectric structure acts as both an insulating element and a programming template that defines the pattern of contact via structures. This multi-functional approach eliminates the need for separate programming steps, as the dielectric structure's presence or absence directly determines the programmed state and guides contact via formation in a single integrated process.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies parameter changes by utilizing variations in material composition (semiconductor vs. dielectric) within the active region to encode information. The programmed state is represented by changing the material parameter - either maintaining epitaxial semiconductor structures or replacing them with dielectric structures. This material parameter change simplifies the programming process compared to traditional methods that rely on complex geometric or positional variations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260059745A1Memory devices programmed with dielectric structures and methods for manufacturing the same
Publication Date: 2026.02.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260059745A1 patent drawing
  • US20260059745A1 patent drawing
  • US20260059745A1 patent drawing

AI summary

A memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store a data bit; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells. The data bit stored by a first one of the plurality of memory cells presents a first logic state when the first memory cell includes a first channel structure, with a first end of the first channel structure connected to a dielectric structure.