Roughened Semiconductor Backside for Low Resistance Contact

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Solution Overview

Problem

Existing packaged electronic devices face challenges in achieving a low resistance contact to the backside of semiconductor device dies, which can lead to delamination issues due to the stress caused by thick metal layers and smooth surfaces post-backgrinding.

Innovation Solution

A thick metal layer with a thickness between 1.5 μm and 5.5 μm is applied to the roughened backside of a semiconductor device die, where the surface roughness is increased from 10 nm to 500 nm through a spin-etching process, enhancing adhesion and preventing delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thick metal layer is applied to achieve low resistance contact, then electrical conductivity is improved, but adhesion deteriorates due to stress causing delamination

Engineering Contradiction:
Improveelectrical conductivityVSAvoidadhesion
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The backside surface of the semiconductor device die is roughened before applying the thick metal layer. This preliminary surface treatment creates anchoring features that prevent delamination caused by stress from the thick metal layer, while still achieving low resistance contact.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The surface roughness parameter is changed from a smooth state (post-backgrinding) to a roughened state with specific Ra values (e.g., 0.03 μm to 0.3 μm). This parameter change enhances adhesion of the thick metal layer without compromising electrical conductivity.

Inventive Principle:
Principle #35Parameter changes

2Strength

If the backside surface is roughened to enhance adhesion, then strength is improved, but surface finish deteriorates

Engineering Contradiction:
ImproveadhesionVSAvoidsurface finish
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

Surface roughening is applied locally to the backside surface of the semiconductor device die, specifically in the regions where metal layers will be deposited. This localized treatment enhances adhesion where needed while maintaining overall surface quality and meeting manufacturing specifications.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The surface roughness is controlled within specific parameter ranges (Ra 0.03 μm to 0.3 μm) to achieve the optimal balance between adhesion enhancement and surface finish quality. This controlled parameter change ensures both improved strength and acceptable manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a low resistance contact that improves transistor performance, reliability, and yield by enhancing the adhesion of the thick metal layer to the silicon substrate, reducing series resistance and preventing delamination.

Implementation Method 1

the surface roughness is increased from 10 nm to 500 nm through a spin-etching process

Methodology Applied
Scientific EffectSurface roughening: Abrasion

Implementation Method 2

provides a low resistance contact that improves transistor performance

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11404385B2Packaged electronic device with low resistance roughened backside contact
Publication Date: 2022.08.02 TEXAS INSTRUMENTS INC
  • US11404385B2 patent drawing
  • US11404385B2 patent drawing
  • US11404385B2 patent drawing

AI summary

In a described example, an electrical apparatus includes: a metal layer formed over a non-device side of a semiconductor device die, the semiconductor device die having devices formed on a device side of the semiconductor device die opposite the non-device side; a first side of the metal layer bonded to a die mount pad on a package substrate; a second side of the metal layer formed over a roughened surface on the non-device side of the semiconductor device die, the roughened surface having an average surface roughness (Ra) between 40 nm and 500 nm; bond pads on the semiconductor device die electrically coupled to conductive leads on the package substrate; and mold compound covering at least a portion of the semiconductor device die and at least a portion of the conductive leads.