Round Robin Bus Arbitration Using Grant History for Fair Access

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Solution Overview

Problem

In computer systems, existing round robin bus arbitration schemes often result in performance issues such as code blocking and task starvation due to a single requester dominating bus access, leading to bottlenecks and inefficiencies.

Innovation Solution

Implementing a round robin bus arbitration method using control vectors and increment/decrement functions, including a request vector (RV), grant history vector (GHV), relative request vector (RRV), and relative grant vector (RGV) to ensure fair access by creating a grant vector (GV) that prevents a single requester from dominating the bus, executed in combinational logic within a single clock cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional round robin bus arbitration is used, then bus access is granted in a sequential manner, but a single requester can dominate bus access leading to code blocking and task starvation

Engineering Contradiction:
Improvefairness of bus accessVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The arbitration scheme dynamically adjusts the round robin sequence based on request patterns. When a requester is granted access, the grant history vector is updated and used to calculate the number of circular shifts, making the arbitration adaptive rather than static. This dynamic adjustment prevents any single requester from monopolizing the bus while maintaining system throughput.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The grant history vector (GHV) stores information about previously granted requests and feeds this back into the arbitration decision process. The number of circular shifts applied to the request vector is determined by the GHV, creating a feedback mechanism that ensures fair distribution of bus access while preventing domination by any single requester.

Inventive Principle:
Principle #23Feedback

2Reliability

If complex arbitration logic is implemented to prevent domination, then fairness is improved, but device complexity increases

Engineering Contradiction:
Improveprevention of bus dominationVSAvoidarbitration logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration logic is segmented into distinct functional components: request vector (RV) for storing current requests, grant history vector (GHV) for storing past grant information, relative request vector (RRV) for shifted request data, and relative grant vector (RGV) for shifted grant data. This segmentation allows each component to perform a specific function, simplifying the overall design while achieving fairness through the coordinated operation of these modular elements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The arbitration scheme changes the parameter of circular shift count based on the grant history. Instead of using a fixed shift pattern, the number of shifts is dynamically determined by the GHV, allowing the system to adapt to different request patterns without increasing structural complexity. This parameter-based control achieves fairness through mathematical transformation rather than complex logical conditions.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple circular shifts are performed to ensure fair access, then access fairness is improved, but access time increases

Engineering Contradiction:
Improveequity of bus allocationVSAvoidbus arbitration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The grant history vector is updated in advance with the identity of the currently granted requester before the next arbitration cycle begins. This preliminary action ensures that the correct number of circular shifts can be applied in the next cycle without requiring complex real-time calculations, thereby reducing arbitration time while maintaining fairness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The arbitration process replaces sequential mechanical checking of each requester with a mathematical transformation approach. By applying circular shifts to the request vector based on the grant history, the system efficiently determines the next requester to be granted access in a single computational step rather than through multiple sequential comparisons, reducing arbitration time while ensuring equitable distribution.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250225093A1Round robin bus arbitration with control vectors and increment and decrement functions
Publication Date: 2025.07.10 SIGNATURE IP CORP
  • US20250225093A1 patent drawing
  • US20250225093A1 patent drawing
  • US20250225093A1 patent drawing

AI summary

Techniques for round robin bus arbitration are disclosed. A plurality of bus requesters is coupled to a common bus by an arbitration logic. Bus access requests are stored in a request vector (RV). A grant history vector (GHV) that contains the last granted requester is checked. A relative request vector (RRV) is created by performing N circular shifts in a right direction until the last granted requester occupies a first bit position in the RRV. The RRV is examined for the first asserted bit beginning with a second bit position in the first direction. A one-hot encoded relative grant vector (RGV) is generated based on the first asserted bit in the RRV. A grant vector (GV) is produced by executing N circular shifts of the RGV in a left direction. Access is granted to the bus requester indicated by the GV.