Semiconductor Package Routing Layer Pitch Transformation
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Solution Overview
Problem
Current semiconductor packaging technologies are unable to efficiently support high IO count devices due to a mismatch between die and package IO pitches, leading to expensive and complex assembly processes, particularly in achieving high data transfer capabilities required for portable computing systems.
Innovation Solution
A semiconductor package with a routing layer having contact elements of different pitches on opposing sides, allowing for electrical connections between semiconductor dice, and a mold structure covering one die, which reduces assembly complexity and cost by using a wafer level assembly process with embedded fine-pitch interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional organic package technology is used, then manufacturing process is simple, but IO pitch is limited to 150 μm which cannot support high IO count devices
Solution Approach 1:
The patent introduces a routing layer positioned between the first and second semiconductor dies, creating an intermediate dimensional plane for signal routing. This allows IO connections to be established through multiple layers (die-to-routing-layer-to-die) rather than direct die-to-die connections, enabling finer pitch connections without increasing assembly complexity at the die level.
Solution Approach 2:
The routing layer acts as an intermediary structure that mediates between the coarse-pitch package level and fine-pitch die level. By providing contact elements on both sides of the routing layer, it enables pitch transformation and facilitates high-density interconnects without requiring complex direct die attachment schemes.
2Adaptability or versatility
If interposer technologies are used to bridge die and package IO mismatch, then IO pitch compatibility is improved, but assembly process becomes expensive and complicated
Solution Approach 1:
The routing layer serves multiple functions simultaneously: it provides pitch transformation, enables electrical routing, offers mechanical support, and facilitates thermal management. This multi-functionality eliminates the need for separate interposer structures, reducing both assembly complexity and cost while maintaining IO pitch compatibility.
Solution Approach 2:
The patent merges the routing function and pitch transformation function into a single integrated routing layer structure, rather than using separate interposer and routing structures. This consolidation simplifies the manufacturing process and reduces assembly steps while achieving the same technical objectives.
3Adaptability or versatility
If first pitch between first electrical die contact elements is greater than second pitch between second electrical die contact elements, then design flexibility is improved, but routing complexity increases
Solution Approach 1:
The routing layer is designed with different contact element densities on different sides to match the specific pitch requirements of each semiconductor die. The first side has contact elements spaced at a larger pitch matching the first die, while the second side has contact elements at a smaller pitch matching the second die, allowing each region to be optimized for its specific connection requirements.
Data Source
AI summary
Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.