Row Decoder Circuit Voltage Control for GIDL Reduction

Solution Overview

Problem

In semiconductor memory devices like DRAM, there is a challenge in reducing Gate-Induced Drain Leakage (GIDL) in sub word drivers during standby time, which is not effectively addressed by existing voltage supply methods.

Innovation Solution

The implementation of a voltage control circuit that selectively supplies an operation voltage lower than normal to the main word driver, while maintaining a higher voltage for the sub word driver to reduce GIDL during standby time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a lower operation voltage is supplied to the main word driver during standby time, then GIDL in sub word drivers is reduced, but the main word driver cannot properly drive the main word line when needed

Engineering Contradiction:
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The decoder circuit is segmented into a main word driver region and sub word driver regions, allowing independent voltage control of each segment. The main word driver receives different voltages than the sub word drivers, enabling selective optimization of GIDL reduction without compromising main word line driving capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different voltage levels are applied to different regions of the decoder circuit based on their specific functional requirements. The main word driver region receives higher voltage when needed for proper driving, while sub word driver regions receive lower voltage during standby to reduce GIDL, achieving local optimization of both parameters.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the decoder circuit area is reduced, then device integration is improved, but proper voltage control for GIDL reduction becomes more difficult

Engineering Contradiction:
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

The sub word driver regions are positioned adjacent to and alongside the main word driver region in a compact nested arrangement. This spatial nesting allows both regions to share common structural elements and wiring, reducing the overall decoder circuit area while maintaining the ability to apply different voltages to each region for effective GIDL control.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250029650A1Semiconductor device having row decoder circuit
Publication Date: 2025.01.23
  • US20250029650A1 patent drawing
  • US20250029650A1 patent drawing
  • US20250029650A1 patent drawing

AI summary

An example apparatus includes: a plurality of first regions each including second and third regions; a plurality of main word driver circuits each configured to activate an associated one of a plurality of main word lines responsive to a row address signal; and a voltage control circuit configured to supply a first power voltage to the plurality of main word driver circuits in a first operation mode and a second power voltage different from the first power voltage to the plurality of main word driver circuits in a second operation mode. One or ones of the plurality of main word driver circuits is arranged in the second region included in each of the plurality of first regions. The voltage control circuit is divided into multiple circuit portions arranged in two or more third regions in two or more of the plurality of first regions, respectively.