Row Decoder Wiring for Nonvolatile Memory Resistance Reduction
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Solution Overview
Problem
Nonvolatile memory devices face challenges in reducing the resistance of conductive lines connecting memory cell blocks to pass transistors, which affects the efficiency and performance of vertically stacked memory devices.
Innovation Solution
The implementation of a nonvolatile memory device with a vertically stacked memory cell array and a row decoder that includes pass transistors, where the row lines are designed with specific wiring configurations, such as parallel wiring and perpendicular contacts, to reduce resistance by varying the width and layout of conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring configurations are used in vertically stacked memory devices, then device complexity is reduced and manufacturing is easier, but resistance of conductive lines increases affecting performance
Solution Approach 1:
The row lines are segmented into multiple separate wiring lines instead of using a single continuous line. Each segment is independently routed and connected through contacts, allowing optimization of each segment's path to reduce overall resistance while maintaining manageable complexity through modular design
Solution Approach 2:
The wiring configuration transitions from a two-dimensional planar layout to a three-dimensional stacked structure. Multiple wiring lines are arranged in different layers and connected vertically through contacts, utilizing the vertical dimension to reduce resistance by creating shorter current paths and parallel conduction channels
2Reliability
If wiring lines are made wider to reduce resistance, then resistance decreases and performance improves, but manufacturing precision requirements increase
Solution Approach 1:
Instead of making a single wide wiring line that would be difficult to manufacture with precise width control, the conductive path is divided into multiple narrower wiring lines. These segments are manufactured using standard precision processes and connected in parallel to achieve the equivalent of a wider line with lower resistance
Solution Approach 2:
Multiple separate wiring lines are electrically merged by connecting them in parallel through contacts. This combining of multiple standard-width lines achieves the low resistance equivalent of a single wide line while avoiding the manufacturing precision challenges of creating and controlling extremely wide single lines
Data Source
AI summary
A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.