Resistive Processing Unit Differential Weight Reading Circuit
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Solution Overview
Problem
Training deep neural networks (DNNs) is computationally intensive and time-consuming, requiring significant resources, with modern neural networks facing limitations due to device specifications in non-volatile memory (NVM) cells, which hinder acceleration despite efforts to reduce horsepower needs and learning times.
Innovation Solution
The development of a resistive processing unit (RPU) that integrates large amounts of resistive RAM directly onto a CPU, enabling differential weight reading through methods involving constant current sources and complementary current sources, allowing for parallel vector-matrix multiplication and local storage and processing of weight values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional microprocessors are used for DNN training, then device specifications and computational resources are utilized, but training is computationally intensive and time-consuming with significant resource requirements
Solution Approach 1:
The patent replaces conventional microprocessor-based digital computation with a resistive processing unit that uses analog electrical currents flowing through resistive RAM devices to perform vector-matrix multiplication. This substitution of computational mechanism enables parallel processing of neural network operations, achieving acceleration of orders of magnitude while reducing training time significantly
Solution Approach 2:
The patent merges storage and processing functions by integrating resistive RAM devices directly onto the CPU, creating a unified resistive processing unit. This consolidation eliminates the memory wall bottleneck by allowing weight values to be stored locally and processed in-place, enabling parallel vector-matrix multiplication without data movement overhead
2Productivity
If conventional microprocessors are used for DNN training, then computational tasks are performed, but power consumption is significant
Solution Approach 1:
The patent replaces energy-intensive digital logic operations in microprocessors with passive analog current flow through resistive devices. The computational throughput is maintained through parallel current flow paths, while power consumption is reduced because resistive devices naturally conduct current without requiring active switching or regeneration, achieving high throughput with lower energy usage
3Productivity
If weight values are stored in non-volatile memory cells, then local storage is achieved, but device specifications limit acceleration capability
Solution Approach 1:
The patent merges the storage function of non-volatile memory with the processing function of the CPU by integrating resistive RAM devices directly into the processor architecture. This combination allows weight values to be stored locally in the same physical substrate as the processing elements, enabling direct access and parallel processing without being constrained by conventional memory interface limitations, thus achieving high acceleration factors
4Measurement precision
If differential weight reading is implemented, then negative, positive or null weights are accurately determined, but circuit complexity increases with constant current sources and complementary FETs
Solution Approach 1:
The patent uses complementary FETs (one N-channel, one P-channel) configured to drive currents in opposite directions through the resistive device. This counterbalancing approach enables differential measurement where the net current directly represents the weight value with its sign information, achieving accurate determination of negative, positive, or zero weights while the complementary structure provides inherent current matching and temperature compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accelerates DNN training by orders of magnitude while reducing power consumption, achieving performance boosts of up to 30,000× compared to state-of-the-art microprocessors and enabling the handling of large-scale Big Data problems that were previously unaddressable.
Implementation Method 1
resistive processing unit (RPU) that integrates large amounts of resistive RAM directly onto a CPU
Data Source
AI summary
A system, comprising: a memory that stores computer-executable components; a processor, operably coupled to the memory, that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise: an expression component that expresses the read current range in an RPU as read current Iwmin and Iwmax, a constant current source component that generates a reference current I, a computing component that subtracts the reference current value within from the read current value to generate an active net current read value that is negative, positive or null; a weighting component that analyzes the active current value and assigns it to a negative, positive or null weight.