RRAM Circuit Bit Current Increase for Resistance State Determination
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Solution Overview
Problem
Conventional RRAM circuits face challenges in precisely determining the resistance state due to insufficient difference in current levels between high and low resistance states, making it difficult to accurately read and perform processes like forming, reset, and set operations.
Innovation Solution
The RRAM circuit design includes multiple RRAM cells and transistors connected in a specific configuration, with optimized voltage and source line coupling to increase bit currents in the low resistance state, allowing for more precise determination of resistance states and improved process completion rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional RRAM circuit configuration is used, then device complexity is reduced, but measurement precision of resistance state deteriorates due to insufficient current level difference
Solution Approach 1:
The patent merges multiple RRAM cells (first RRAM cell and second RRAM cell) into a single circuit block that shares common transistors (first transistor and second transistor). This configuration allows the circuit to achieve higher current levels for better measurement precision while reusing transistor components, thereby managing device complexity through resource sharing rather than complete duplication.
2Measurement precision
If bit current in low resistance state is increased, then measurement precision improves, but use of energy increases
Solution Approach 1:
The patent implements dynamic control of bit current through transistor gating mechanisms. The first transistor and second transistor can be selectively activated or deactivated based on the resistance state being measured. During read operations, the transistors dynamically adjust the current flow to achieve sufficient current levels for accurate measurement while minimizing unnecessary energy consumption when high current is not required.
Data Source
AI summary
An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.