RRAM Buffer Layer for Void-Free Dielectric Etching
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Solution Overview
Problem
Conventional resistive random access memory (RRAM) manufacturing faces challenges with low dielectric constant materials used in peripheral regions, leading to voids between memory cells, operation errors, and increased production complexity and cost due to differing etching processes required for array and peripheral regions.
Innovation Solution
A RRAM structure and manufacturing method that includes a buffer layer in the array region to enhance mechanical strength and protect memory cells, allowing for the use of different dielectric materials in the array and peripheral regions, enabling simultaneous etching processes and improving yield and reliability without increasing production complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k dielectric material is used in the peripheral region to increase operating speed, then the operating speed of logic circuits is improved, but voids form between memory cells due to poor gap-filling ability
Solution Approach 1:
The patent applies different dielectric materials to different regions: low-k dielectric material is used in the peripheral region for high-speed logic circuits, while gap-filling dielectric material is used in the array region to fill spaces between memory cells without forming voids. This local differentiation resolves the contradiction by allowing each region to have the material properties optimal for its function.
2Reliability
If different etching processes are used for array region and peripheral region to accommodate different opening depths, then the memory cells are protected from excessive etching, but the process complexity and production cost increase significantly
Solution Approach 1:
The patent introduces a buffer layer in the array region before the etching process. This buffer layer serves as a protective barrier that prevents excessive etching of memory cells. By performing this preliminary protective action, the patent enables the use of a single etching process for both regions, reducing process complexity while maintaining memory cell integrity.
3Ease of manufacture
If a single dielectric material is used for both array and peripheral regions, then the manufacturing process is simplified, but the performance requirements of both high-speed operation and void-free filling cannot be simultaneously met
Solution Approach 1:
The patent implements regional differentiation by using gap-filling dielectric material in the array region to ensure void-free filling between memory cells, and low-k dielectric material in the peripheral region to enable high-speed logic circuit operation. This local quality approach allows the manufacturing process to meet different performance requirements in different regions while remaining practical to implement.
Data Source
AI summary
A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes a substrate having an array region and a peripheral region. A plurality of memory cells and a gap-filling dielectric layer overlying the memory cells are located on the substrate and in the array region. A buffer layer only in the array region covers the gap-filling dielectric layer, and its material layer is different from that of the gap-filling dielectric layer. A first low-k dielectric layer is only located in the peripheral region, and its material is different from that of the buffer layer. A dielectric constant of the first low-k dielectric layer is less than 3. A top surface of the first low-k dielectric layer is coplanar with that of the buffer layer. A first conductive plug passes through the buffer layer and the gap-filling dielectric layer and contacts one of the memory cells.