RRAM Cell Structure Patterning With Lower Metal Line Etch Stop

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Solution Overview

Problem

The formation of a memory structure in advanced semiconductor devices, such as RRAM devices, using a silicon carbide layer as an etch stop can lead to increased likelihood of shorting between metal lines and upper electrode structures due to reduced isolation distance, affecting device performance and reliability.

Innovation Solution

Utilizing the metal line below the cell structure as an etch stop instead of silicon carbide, which reduces the overall height of the memory structure and maintains or increases the isolation distance, thereby reducing the risk of shorting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a silicon carbide layer is used as an etch stop during memory structure formation, then the cell structure can be properly patterned, but the isolation distance between metal lines and electrodes is reduced, increasing the likelihood of shorting

Engineering Contradiction:
Improvecell structure patterningVSAvoidisolation distance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Instead of using a silicon carbide layer as the etch stop (conventional approach), the patent inverts the approach by using the lower metal line structure itself as the etch stop. This reversal eliminates the need for the silicon carbide layer and prevents the isolation distance reduction problem while still achieving proper cell structure patterning.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and removes the silicon carbide layer from the etch stop function, eliminating the source of the problem. By taking out the problematic silicon carbide layer and replacing its etch stop function with the lower metal line structure, the patent resolves the contradiction between manufacturing precision and reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

2Manufacturing precision

If a silicon carbide layer is used as an etch stop, then etching can be controlled, but the overall height of the memory structure increases and isolation distance is reduced

Engineering Contradiction:
Improveetching controlVSAvoidmemory structure height
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent removes the silicon carbide layer from the structure, thereby eliminating the extra height it adds. By extracting this layer and using the lower metal line structure as the etch stop instead, the patent achieves both etching control and reduced memory structure height.

Inventive Principle:
Principle #2Taking out (Extraction)

3Length of stationary object

If the isolation distance is reduced to decrease memory structure height, then device size is reduced, but the likelihood of shorting between metal lines and electrodes increases

Engineering Contradiction:
Improvememory structure heightVSAvoidshorting risk
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent inverts the conventional approach by not reducing the isolation distance through silicon carbide layer removal. Instead, it uses the lower metal line structure as the etch stop, which naturally maintains adequate isolation distance while achieving compact memory structure height through alternative means.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12604677B2Semiconductor device and methods of manufacturing
Publication Date: 2026.04.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12604677B2 patent drawing
  • US12604677B2 patent drawing
  • US12604677B2 patent drawing

AI summary

A cell structure of a memory device includes an upper electrode structure separated from a metal line above the cell structure by a combination of one or more layers including an isolation layer. The cell structure may be patterned using a metal line below the cell structure as an etch-stop layer. Relative to other techniques that include patterning the cell structure using a silicon carbide layer located over the metal line below the cell structure as an etch-stop layer, the techniques described herein may reduce an overall height of the memory structure. Additionally, or alternatively, the techniques may maintain or increase an isolation distance between the metal line above the cell structure and the upper electrode structure. In this way, a likelihood of shorting between the metal line above the cell structure and the upper electrode structure is reduced to improve a performance and/or a reliability of the memory device.