RRAM Cell Conductive Etch-Stop Layer for Planar Topography
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Solution Overview
Problem
Traditional RRAM cell manufacturing involves complex mask patterning and etching steps, leading to uneven topography and non-volatile copper etching by-products, which complicates the formation of bottom electrodes and contaminates the cell chamber.
Innovation Solution
Incorporating a conductive etch-stop layer between the lower metal interconnect and bottom electrode, which allows for a planar topography and eliminates the need for chemical mechanical polishing, reducing mask patterning steps and minimizing copper etching by-products through selective etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional mask patterning and etching steps are used to form bottom electrodes, then the RRAM cell structure can be formed, but uneven topography is created and copper etching by-products contaminate the cell chamber
Solution Approach 1:
A conductive etch-stop layer is introduced as an intermediary between the copper interconnect and the bottom electrode. This layer acts as a protective barrier during etching operations, preventing copper particles from contaminating the cell chamber while still allowing the bottom electrode to be properly formed. The etch-stop layer is selectively removed after the electrode formation is complete.
Solution Approach 2:
The conductive etch-stop layer is deposited in advance before the bottom electrode formation process. This preliminary action prepares the structure to withstand subsequent etching operations without generating contamination, enabling a cleaner manufacturing process from the outset.
2Ease of manufacture
If traditional mask patterning and etching steps are used, then bottom electrodes can be formed, but complex mask patterning steps are required
Solution Approach 1:
The conductive etch-stop layer serves as a sacrificial intermediary that simplifies the patterning process. By providing a distinct etch-stop interface, it enables simpler mask patterns to define the bottom electrode geometry without requiring complex multi-step patterning sequences.
Solution Approach 2:
The formation process is segmented into distinct stages: first forming the etch-stop layer, then forming the bottom electrode with simplified patterning, and finally removing the etch-stop layer. This segmentation allows each step to be optimized independently, reducing overall process complexity.
3Shape
If traditional etching processes are used, then bottom electrodes can be formed, but chemical mechanical polishing is required to achieve planar topography
Solution Approach 1:
The conductive etch-stop layer acts as a planarizing intermediary that provides a flat reference surface during electrode formation. This eliminates the need for subsequent CMP processes to achieve planar topography, as the etch-stop layer itself ensures uniform surfaces throughout the fabrication process.
Solution Approach 2:
Planar topography is achieved as a preliminary result of depositing the conductive etch-stop layer, before any electrode formation occurs. This preliminary planarization eliminates the need for post-processing CMP steps to correct topography issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the RRAM cell structure, protects the low-k dielectric layer, and reduces contamination, enabling more efficient and straightforward manufacturing without the need for CMP processes and fewer mask steps.
Implementation Method 1
The CESL has an etch-selectivity different from that of the bottom electrode and the first metal interconnect structure
Data Source
AI summary
The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.