RRAM Data Storage Layer Vertical Height Extension
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Solution Overview
Problem
As RRAM cell geometries shrink with successive technology generations, the forming voltage required to establish conductive filaments increases, posing a reliability concern due to higher gate oxide stress, necessitating a reduction in forming voltage levels.
Innovation Solution
Increasing the height of the data storage layer in RRAM cells to expand its area without increasing the lateral dimensions, allowing for the use of lower forming voltages by vertically extending the data storage layer between metal interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the lateral dimensions of RRAM cells are reduced to shrink cell geometry, then the cell size is reduced, but the forming voltage increases causing higher gate oxide stress
Solution Approach 1:
The patent applies dimensionality change by extending the data storage layer vertically in the z-dimension rather than laterally in the x-y plane. The data storage layer height is increased to span multiple metal interconnect layers (e.g., from one layer to three or more layers vertically), thereby increasing the effective storage area without increasing the lateral cell footprint. This vertical extension reduces the forming voltage and gate oxide stress while maintaining small lateral dimensions.
2Reliability
If the data storage layer height is increased to expand storage area, then the forming voltage is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent applies multi-functionality by having the vertically extended data storage layer serve multiple functions simultaneously: it provides increased storage area, acts as the resistive switching medium across multiple metal interconnect layers, and enables lower forming voltage operation. The same vertical structure that increases area also reduces stress on gate oxide, making the structure universally beneficial for both capacity and reliability.
3Area of moving object
If the data storage layer height is increased vertically, then the area for data storage is increased, but the spacing between metal interconnect layers must be sufficient
Solution Approach 1:
The patent utilizes the vertical dimension to increase data storage area by extending the data storage layer height to span multiple metal interconnect layers. This vertical stacking approach allows the storage layer to occupy the z-dimension between widely spaced metal layers, effectively converting lateral area constraints into vertical space utilization. The data storage layer can extend from a first metal interconnect layer through a second and third metal interconnect layer, maximizing area without requiring reduced lateral dimensions or increased metal layer spacing.
Data Source
AI summary
The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.