Dedicated Electroforming Contacts for RRAM Switching Resistance
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Solution Overview
Problem
Conventional RRAM devices have low switching resistance due to strong conductive filaments formed during electroforming, which is undesirable for large-scale memory arrays, and current limiting methods like FETs increase the footprint of memory cells.
Innovation Solution
The implementation of dedicated electroforming contacts within RRAM arrays allows for controlled electroforming of resistive memory cells, limiting the size and strength of conductive filaments to achieve high switching resistance, enabling the fabrication of larger RRAM crossbar arrays with reduced voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electroforming process is used to form conductive filament in metal-oxide layer, then memory cell can be initialized with resistive switching properties, but switching resistance is low (kOhm range) which is undesirable for large-scale memory arrays
Solution Approach 1:
The patent segments the electroforming process into two distinct phases: a first electroforming process that forms an initial conductive filament, and a second electroforming process that modifies the filament to achieve desired resistance. This segmentation allows independent optimization of filament formation and resistance control, resolving the contradiction between reliable switching and array scalability.
Solution Approach 2:
The first electroforming process performs a preliminary action by forming an initial conductive filament with higher resistance than conventional processes. This preliminary filament structure serves as a controlled foundation for the second electroforming process, which then adjusts the resistance to target values in the MOhms range, enabling both reliable switching and large-scale array operation.
2Ease of operation
If current limiting FET device is integrated with each memory cell to limit current during electroforming, then current can be controlled, but footprint of memory array increases significantly
Solution Approach 1:
The patent extracts the current limiting function from the memory cell structure itself and relocates it to external circuitry. By removing the FET device integration requirement, the memory cell footprint is reduced while current control during electroforming is maintained through external current limiting circuits, resolving the contradiction between ease of operation and compact area.
Solution Approach 2:
The patent implements a universal electroforming approach where a single memory cell structure can be used across the entire array without requiring individual current limiting devices. The external current limiting circuit serves all memory cells universally, enabling compact footprint while maintaining controlled electroforming processes across large-scale arrays.
3Quantity of substance
If large-scale RRAM crossbar arrays are fabricated, then memory capacity increases, but voltage drops across long crossbar wiring become significant
Solution Approach 1:
The patent changes the resistance parameter of the memory cell from conventional kOhm range to MOhms range through the two-phase electroforming process. This parameter change increases the memory cell resistance relative to the crossbar wiring resistance, reducing the proportion of voltage drop across the wiring and enabling large-scale arrays with significant memory capacity while minimizing energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of RRAM memory cells with higher switching resistance (MOhms) suitable for large-scale arrays, reducing the footprint and voltage drops across long crossbar wiring, while maintaining controlled electroforming processes.
Implementation Method 1
an "electroforming" process is performed to form a conductive filament in the metal-oxide layer
Implementation Method 2
the insulator layer (e.g., metal-oxide) exhibits a resistive switching behavior
Implementation Method 3
certain techniques can be utilized to control the current that is applied to the memory cells during an electroforming process
Data Source
AI summary
Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.