RRAM Bottom Electrode Design for 3D Stacking and Field Control
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Solution Overview
Problem
Conventional resistive random access memory (RRAM) devices face challenges in miniaturization, reliability, and compatibility with silicon processes, particularly in three-dimensional stacking and integration with peripheral circuit elements, due to uneven electric field distribution and high reset currents.
Innovation Solution
A resistive memory device is fabricated using a doped semiconductor bottom electrode with electric field concentration regions, a resistance change layer, and a metal top electrode, allowing for three-dimensional stacking and compatibility with CMOS processes, reducing operating voltage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional MIM structure with flat metal-insulator interface is used, then the device structure is simple, but the electric field is evenly distributed causing poor control over conductive filament formation and high reset current
Solution Approach 1:
The bottom electrode is designed with localized high-resistivity regions that create non-uniform electric field distribution. This local modification of electrode properties enables precise control over conductive filament formation positions and reduces reset current, while maintaining overall structural simplicity
Solution Approach 2:
The resistivity of the bottom electrode is modified in specific regions through doping or material composition changes. This parameter change creates electric field concentration zones that guide conductive filament formation, improving manufacturing precision without significantly increasing device complexity
2Volume of moving object
If device size is reduced to 20 nm or less for miniaturization, then integration density increases, but reliability problems arise
Solution Approach 1:
At scaled dimensions of 20 nm or less, the bottom electrode incorporates localized high-resistivity regions that create controlled electric field distribution. This local quality modification ensures reliable conductive filament formation and stability even at reduced device size, maintaining reliability while achieving miniaturization
Solution Approach 2:
The patent introduces vertical stacking of multiple RRAM cells to achieve miniaturization in the vertical dimension rather than further reducing lateral dimensions. This dimensional transition maintains manufacturing reliability while achieving higher integration density
3Ease of manufacture
If conventional MIM structure is used, then fabrication process is simple, but compatibility with silicon process and peripheral circuit elements is limited
Solution Approach 1:
The bottom electrode is designed to serve multiple functions: it acts as both the electrical electrode and an integral part of the CMOS fabrication process. By using doped semiconductor material that can be formed using standard CMOS doping and deposition techniques, the structure achieves compatibility with silicon processes and peripheral circuit elements while maintaining ease of manufacture
Solution Approach 2:
The bottom electrode uses composite material structure combining semiconductor material with doped regions. This composite approach enables compatibility with silicon-based CMOS processes while maintaining the electrical properties needed for RRAM operation, bridging the gap between simplicity and adaptability
4Productivity
If three-dimensional vertical stacked array is implemented, then integration density increases, but leakage current from adjacent cells affects read operation
Solution Approach 1:
In vertically stacked arrays, each RRAM cell incorporates localized high-resistivity regions in the bottom electrode that create confined electric field distribution. This local quality control prevents electric field leakage to adjacent cells, eliminating leakage current issues while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent implements three-dimensional vertical stacking of multiple RRAM cells to achieve high integration density. By carefully designing the vertical electric field confinement through localized electrode modifications, leakage current between stacked cells is prevented, enabling reliable operation of densely integrated 3D arrays
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances control over conductive filament formation, reduces reset current, and enables vertical stacking, improving the reliability and integration of RRAM devices while reducing power consumption and facilitating next-generation computing applications.
Implementation Method 1
the bottom electrode has one or more electric field concentration regions toward the resistance change layer
Implementation Method 2
a resistance change layer is formed in the top electrode by the oxidation reaction
Implementation Method 3
the threshold switch layer having the properties of the conductor is formed by growth from the bottom electrode changing the oxygen deficiency (oxygen vacancies) state by the thermal energy applied with the voltage
Data Source
AI summary
The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.