RRAM Memory Array Architecture with Segmented Electroforming
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices, particularly those based on amorphous silicon, face endurance issues due to excessive bias voltage during write and erase cycles, leading to shortened lifespan and yield problems during the electroforming process.
Innovation Solution
A memory array architecture incorporating two-terminal memory cells, including RRAM, with a switching medium of amorphous silicon, where the resistance is controlled by applying program and erase voltages to form and retrieve conductive filaments, utilizing silver as a filament-forming ion source and boron-doped polysilicon electrodes, enabling efficient programming, reading, and erasing without affecting neighboring cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If excessive bias voltage is applied during write and erase cycles, then programming speed is improved, but device endurance is shortened
Solution Approach 1:
The patent segments the voltage application process into distinct phases: a high-voltage electroforming phase to create conductive filaments, followed by lower-voltage read and verify phases. This segmentation allows rapid initial programming while protecting the device from continuous high-voltage stress that would degrade endurance.
Solution Approach 2:
The electroforming process is performed as a preliminary action before normal read/verify operations. By pre-forming the conductive filaments through a controlled high-voltage pulse, subsequent operations can proceed at lower voltages, improving endurance while maintaining programming effectiveness.
2Manufacturing precision
If high voltage is applied during electroforming, then conductive path formation is achieved, but device yield is reduced
Solution Approach 1:
The patent carefully controls the parameters of the electroforming voltage pulse, including its magnitude, duration, and waveform. By optimizing these parameters, the process achieves reliable conductive path formation while minimizing damage to the device structure, thereby improving yield.
Solution Approach 2:
The patent uses an amorphous silicon layer as an intermediary medium during electroforming. This layer facilitates controlled ion migration and conductive filament formation while protecting the underlying substrate from the full stress of the high-voltage pulse, preserving device yield.
3Manufacturing precision
If more metal ions are moved during write cycles, then resistance switching is achieved, but Joule heating increases
Solution Approach 1:
The patent employs periodic voltage pulsing during the write process, alternating between high-voltage pulses that drive ion migration and lower-voltage intervals that allow heat dissipation. This periodic action achieves effective resistance switching while controlling Joule heating through controlled thermal relaxation cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the endurance and yield of RRAM devices by effectively managing the formation and retrieval of conductive filaments, allowing for reliable low-voltage read processes and maintaining resistance states for non-volatile data storage with improved resistance ratios between ON and OFF states.
Implementation Method 1
The resistance switching has been explained by the formation of conductive filaments inside the insulator layer due to Joule heating and electrochemical processes in binary oxides (e.g. NiO and TiO2)
Implementation Method 2
In the case of a-Si structures, electric field-induced diffusion of metal ions into the silicon leads to the formation of conductive filaments that reduce the resistance of the a-Si structure
Implementation Method 3
The resistance switching has also been explained by field assisted diffusion of ions in TiO2 and amorphous silicon (a-Si) films
Data Source
AI summary
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.