RRAM Cell Structure with Nanosheet Resistor Integration
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Solution Overview
Problem
The challenge in integrated circuits is forming effective memory cells at smaller technology nodes due to difficulties in ensuring proper feature formation using thin-film deposition and etching techniques.
Innovation Solution
The integration of a gate all around transistor and resistor device in overlapping process steps, utilizing similar structures and materials, reduces the number of additional steps and allows for smaller feature sizes, with the resistor device acting as a memory storage element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If thin-film deposition and etching techniques are used to decrease feature size, then the number of transistors per area increases, but the reliability of proper feature formation deteriorates
Solution Approach 1:
The patent merges the formation of the resistor device and transistor into a single integrated structure formed by the same processing steps. The resistive element, gate dielectric layer, and gate electrode are formed simultaneously for both devices, eliminating the need for separate processing sequences and reducing the risk of formation defects at scaled dimensions.
Solution Approach 2:
The gate all-around transistor structure serves dual functions: as a transistor for memory cell operation and as a resistor device for memory storage. The same gate dielectric layer and gate electrode structure provide both transistor gating functionality and resistive element formation, enabling universal processing for both device types.
2Manufacturing precision
If additional processing steps are added to ensure proper feature formation, then manufacturing precision improves, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines the resistor device and transistor formation into overlapping process steps where the same deposition and etching sequences create both structures. The gate dielectric layer and gate electrode are formed in a single processing sequence that simultaneously defines both the transistor gate and the resistive element, reducing total processing steps while maintaining precision.
3Area of moving object
If feature size is reduced to increase memory density, then the number of memory cells per area increases, but the difficulty of forming effective memory cells increases
Solution Approach 1:
The patent merges the resistor device and transistor into a single integrated structure formed by the same processing steps. The resistive element, gate dielectric layer, and gate electrode are formed simultaneously for both devices, eliminating the need for separate processing sequences and reducing the risk of formation defects at scaled dimensions.
Data Source
AI summary
A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.