Selective Barrier Layer Growth for RRAM Crossbar Arrays
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Solution Overview
Problem
Resistive random access memory (RRAM) crossbar arrays face challenges in protecting their stacks within a semiconductor device, particularly in maintaining high electrode conductivity while minimizing the active device area for neuromorphic computing and high-density memory applications.
Innovation Solution
A method involving the formation of a self-aligned barrier layer selectively grown over conductive lines in the RRAM crossbar array area, ensuring the periphery remains unaffected, which allows for high conductivity and a small active area by maximizing electrode cross-section and minimizing contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed over conductive lines in RRAM crossbar arrays, then electrode conductivity is improved, but active device area increases
Solution Approach 1:
The barrier layer is selectively formed only in the RRAM crossbar array area where conductive lines intersect with memory stacks, rather than uniformly across the entire substrate. This localized approach provides necessary electrical isolation and conductivity control at critical interfaces while leaving peripheral areas unaffected, thus maintaining high electrode conductivity where needed without unnecessarily expanding the active device area.
Solution Approach 2:
The barrier layer formation process is segmented into specific regions: it is applied only over conductive lines within the RRAM crossbar array footprint, excluding peripheral circuit areas. This segmentation allows the barrier layer to provide its protective and conductive functions precisely where required by the memory stacks, while minimizing the overall area occupied by barrier layer structures.
2Reliability
If the barrier layer is formed to protect RRAM stacks, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The barrier layer is formed as a preliminary step before subsequent RRAM stack formation processes. By establishing the barrier layer early in the fabrication sequence, the patent simplifies later processing steps and prevents contamination or damage to underlying structures, thereby improving overall device reliability without adding significant complexity to the manufacturing workflow.
Solution Approach 2:
The barrier layer serves as an intermediary structure between the conductive lines and the RRAM stack materials. This intermediate layer provides necessary electrical isolation, prevents unwanted diffusion or reaction between adjacent materials, and controls interfacial properties, thereby protecting the RRAM stacks and improving device reliability while maintaining a relatively simple manufacturing process.
Data Source
AI summary
A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer.