RRAM Array Source Line Sharing for Voltage Uniformity
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Solution Overview
Problem
Bipolar-type resistive memory arrays face challenges in achieving high area efficiency and reliability due to the need for bidirectional write voltage application, which results in increased source line resistance and voltage dispersion, making it difficult to maintain uniform voltages across memory cells.
Innovation Solution
The implementation of a memory array structure where a single source line is shared by multiple bit lines, with a second source line extending orthogonally to the bit lines, allowing for improved area efficiency and reduced source line resistance, while maintaining uniform voltage application across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated source line is arranged for one bit line in bipolar-type resistive memory, then the write voltage can be applied bidirectionally, but the source line resistance increases and voltage dispersion occurs
Solution Approach 1:
The source line is segmented into multiple independent source lines, with each source line serving a specific bit line. This segmentation reduces the length and resistance of each individual source line, thereby minimizing voltage dispersion and improving write voltage uniformity across memory cells.
Solution Approach 2:
Each source line is designed to serve multiple functions: it acts as a voltage supply line for write operations, a current path for read operations, and a reference for voltage balancing. This multi-functionality allows the source line structure to be optimized for both read and write operations simultaneously.
2Reliability
If the source line extends in the same direction as the bit line, then bidirectional write voltage can be applied, but the area efficiency decreases
Solution Approach 1:
The source lines are arranged in a direction orthogonal to the bit lines, transitioning from a one-dimensional parallel arrangement to a two-dimensional grid structure. This dimensional change allows for more efficient space utilization while maintaining the bidirectional write capability through the orthogonal intersection of bit and source lines.
3Area of stationary object
If the line width of the source line is reduced to improve area efficiency, then the area decreases, but the source line resistance increases
Solution Approach 1:
By segmenting the source lines into multiple shorter segments rather than using one long source line, the resistance of each segment is reduced. This allows the use of narrower line widths for area efficiency while maintaining low resistance through the segmented structure.
Solution Approach 2:
Multiple source lines are combined in parallel to provide sufficient current capacity while maintaining low resistance. The parallel combination of multiple narrow source lines achieves the same current-carrying capacity as a single wide source line but with reduced area and resistance.
Data Source
AI summary
A resistive random access memory with superior area efficiency and higher reliability is provided. The resistive random access memory RRAM in the present invention includes a memory array, which includes a plurality of memory cells MC arranged in rows and columns. Each memory cell MC includes a variable resistive element and an access transistor. Gates of the access transistors in a column are connected to a word line WL. First electrodes of the variable resistive element in a row are connected to a bit line BL. Second electrodes of the variable resistive element in the row are connected to a source line SL. The source line SL includes a local source line 250, which extends in a direction that is orthogonal to the bit lines BL0/BL1/BL2/BL3 and is shared by the bit lines BL0/BL1/BL2/BL3.