Spacer-Based Self-Aligned Etching for RRAM Element Alignment
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Solution Overview
Problem
Traditional methods for patterning resistive and conductive elements in resistive random access memory (RRAM) using lithography techniques result in element misalignment and mismatching, leading to increased resistance and performance issues due to rough and jagged edges and mismatched contact surfaces.
Innovation Solution
A method involving the formation of spacers and patterning of resistive and conductive layers using a single mask, with spacers acting as masks for etching, to align and match contact surfaces of resistive and conductive elements, eliminating the need for traditional lithography and photoresist techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography techniques (electron-beam or EUV) are used to pattern resistive and conductive elements, then manufacturing capability is achieved, but element misalignment and mismatching occur leading to increased resistance
Solution Approach 1:
The patent segments the patterning process into multiple steps using spacer-based self-aligned etching. Instead of patterning all elements in a single lithography step, the method divides the process into sequential etching steps where spacers are formed and used as masks for subsequent etching operations, achieving better alignment precision through process segmentation
Solution Approach 2:
The patent applies preliminary action by forming spacers before the final patterning step. The spacers are deposited and patterned in advance to serve as self-aligned masks, ensuring that the conductive and resistive elements are etched with precise alignment before the actual element formation occurs
2Ease of manufacture
If separate patterning processes are used for resistive and conductive elements, then manufacturing flexibility is maintained, but element mismatching occurs with different contact surface shapes
Solution Approach 1:
The patent merges the patterning of resistive and conductive elements into a unified self-aligned process. By using spacers as common masks for both etching steps, the method ensures that both element types are patterned with identical geometries and matching contact surfaces, eliminating the mismatching problem while maintaining manufacturing flexibility
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the lithography pattern and the final element geometry. These spacers serve as self-aligned masks that transfer the pattern to both resistive and conductive elements simultaneously, ensuring geometric matching without requiring separate patterning processes
3Ease of manufacture
If lithography with photoresist is used, then patterning capability is achieved, but rough and jagged edges are created increasing resistance
Solution Approach 1:
The patent replaces the mechanical/photochemical lithography system with a spacer-based self-aligned etching system. Instead of relying on photoresist coating and development processes that create rough edges, the method uses deposited spacer layers and controlled etching processes that produce smooth element edges, substituting the lithography mechanism with a different fabrication approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes element misalignment and mismatching, reducing resistance and improving the reliability and performance of RRAM by ensuring precise alignment and matching contact surfaces of resistive and conductive elements.
Implementation Method 1
etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder
Data Source
AI summary
A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.