RRAM Bottom Electrode Substrate Integration
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Solution Overview
Problem
The fabrication of RRAM devices using traditional layer-by-layer approaches is challenging for integration into modern CMOS processing due to height differences with other structures, leading to patterning errors and additional processing steps.
Innovation Solution
The use of CMOS-compatible processes to form RRAM cells with metal silicide electrodes and insulating layers, where the bottom electrode is partially formed within the substrate, reducing height discrepancies and simplifying integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional layer-by-layer approach is used to fabricate RRAM devices, then the device structure can be formed with discrete deposition, lithography and etching steps, but the overall height of the RRAM device becomes greater than the height of other CMOS structures, leading to patterning errors and additional processing steps
Solution Approach 1:
The patent merges the RRAM device fabrication with the existing CMOS processing steps by forming the bottom electrode simultaneously with the source/drain regions during the same ion implantation and silicidation processes. This integration eliminates the need for separate deposition and lithography steps for the bottom electrode, allowing the RRAM device to conform to the CMOS process flow and avoid height discrepancies that cause patterning errors.
Solution Approach 2:
The bottom electrode structure serves multiple functions: it acts as both the RRAM device electrode and the source/drain region for the associated transistor. This multi-functionality allows a single structure to fulfill both roles, eliminating the need for separate processing steps and reducing the overall device height to match CMOS standards.
2Ease of manufacture
If traditional layer-by-layer approach is used to fabricate RRAM devices, then the device structure can be formed with discrete deposition, lithography and etching steps, but additional processing steps are required to address height differences
Solution Approach 1:
The patent combines the formation of the RRAM bottom electrode with the CMOS source/drain region fabrication by using the same ion implantation and silicidation processes. This merging eliminates the need for separate deposition, lithography, and etching steps that would otherwise be required, thereby reducing device complexity while maintaining ease of manufacture through standard CMOS processes.
3Manufacturing precision
If bottom electrode is formed within the substrate using CMOS-compatible processes, then height discrepancies are reduced and integration is simplified, but the electrode must be positioned below the top electrode width
Solution Approach 1:
The bottom electrode is nested within the substrate and positioned below the top electrode width, with the top electrode extending beyond the bottom electrode boundaries. This nested configuration allows the bottom electrode to be formed by ion implantation into the substrate while the top electrode is deposited above, creating a structure where the electrodes are offset in both position and depth, thereby achieving precise integration without requiring complex positioning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of RRAM devices into CMOS integrated circuits, minimizing patterning errors and reducing the need for additional processing steps, thereby enhancing fabrication efficiency.
Implementation Method 1
fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes
Data Source
AI summary
Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.