RRAM Through-Hole Structure for Single-Mask BEOL Integration
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Solution Overview
Problem
The existing method of manufacturing resistive random access memories (RRAMs) has low compatibility with logic back-end processes and requires three photomasks, resulting in high production costs.
Innovation Solution
A resistive random access memory structure is designed with a first inter-layer dielectric layer, a bottom electrode, a capping layer, and a through hole that partially exposes the bottom electrode, where a variable resistance layer comprising tantalum oxide layers is formed within the hole, and a top electrode is deposited, with an iridium layer between the top electrode and the variable resistance layer, all covered by a second inter-layer dielectric layer, reducing the need for additional photomasks and enhancing compatibility with logic back-end processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the existing method of manufacturing RRAMs is used, then the protective layer can be formed, but three photomasks are required resulting in high production cost and low compatibility with logic back-end process
Solution Approach 1:
The patent merges the protective layer formation with the existing logic back-end process by using a single photomask to define both the protective layer pattern and the RRAM cell structure. This integration eliminates the need for separate photomasks and simplifies the manufacturing workflow, directly addressing the contradiction between ease of manufacture and device complexity.
Solution Approach 2:
The single photomask serves multiple functions: it defines the protective layer pattern, establishes the RRAM cell boundaries, and guides subsequent fabrication steps. This multi-functionality reduces the total number of photomasks required from three to one, thereby reducing production cost and improving compatibility with logic back-end processes.
2Manufacturing precision
If three photomasks are used to form the protective layer, then the protective layer can be accurately formed, but the production cost increases
Solution Approach 1:
The patent combines the protective layer formation step with the RRAM cell definition step using a single photomask. This merging maintains manufacturing precision by ensuring that the protective layer pattern is directly aligned with the RRAM cell structure, while simultaneously reducing production cost by eliminating the need for two additional photomasks.
Solution Approach 2:
The single photomask is used to pre-define both the protective layer pattern and the RRAM cell structure in advance. This preliminary action ensures that subsequent fabrication steps automatically inherit the correct patterns, maintaining precision while reducing the overall number of photomask operations required and thereby lowering production cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the compatibility of RRAM fabrication with logic back-end processes, reduces production costs by eliminating the need for extra photomasks, and ensures effective protection of the RRAM structure during manufacturing.
Implementation Method 1
Resistive random access memories (RRAMs) are non-volatile memory devices using changes in resistance characteristics of a material to store data
Implementation Method 2
A protection layer may be adjacent to the RRAM cell to protect the RRAM cell from being damaged during the manufacturing process
Implementation Method 3
the iridium layer conformally covers the top surface of the capping layer, a sidewall of the capping layer above the top surface of the tantalum oxide (Ta2O5) layer, and the top surface of the tantalum oxide (Ta2O5) layer
Data Source
AI summary
A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.


