RSA Acceleration Processor Instruction for 64-bit Multiplication
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Solution Overview
Problem
The RSA algorithm, widely used for public-key cryptography, is computationally intensive, particularly in its implementation using the OpenSSL library, where functions like bn_mul_mont consume significant execution time due to specific instructions that contribute to overall processing delays.
Innovation Solution
The introduction of RSA acceleration instructions that combine multiple instructions into a single operation, such as the RSAFMAA128 instruction, which multiplies and adds 64-bit values efficiently, reducing the need for separate 64-bit and 128-bit operations and optimizing the execution time by eliminating redundant instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional OpenSSL library implementation is used, then software compatibility is maintained, but execution time increases and processing speed decreases
Solution Approach 1:
The patent segments the RSA algorithm implementation into distinct functional units within the processor architecture. Specific execution units are dedicated to cryptographic operations, separating them from general-purpose computing resources. This segmentation allows optimized handling of RSA-specific instructions while maintaining compatibility with standard OpenSSL library calls, thereby improving processing speed without sacrificing software compatibility.
Solution Approach 2:
The patent changes the operational parameters of the processor by introducing new instruction set extensions and optimizing internal operation parameters for cryptographic workloads. The processor detects when RSA operations are being performed and dynamically adjusts its operational mode to prioritize these operations, changing timing parameters and resource allocation to minimize execution time for cryptographic functions while maintaining standard behavior for other operations.
2Productivity
If multiple separate instructions are used for 64-bit and 128-bit operations, then computational accuracy is maintained, but device complexity increases and processing efficiency decreases
Solution Approach 1:
The patent merges multiple separate instructions into unified cryptographic instruction operations. Instead of requiring separate instructions for 64-bit multiplication, 128-bit multiplication, addition, and carry handling, the patent introduces consolidated instructions that perform these operations atomically. This merging reduces the total number of instructions needed, simplifies the instruction stream, and improves processing efficiency while maintaining the same computational accuracy through integrated multi-precision arithmetic units.
Data Source
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AI summary
A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.