RTL Congestion Prediction Engine for IC Routing
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Solution Overview
Problem
The physical implementation of integrated circuit (IC) designs often faces routing congestion failures, leading to increased time and cost, reduced performance, and potential design incompatibility with chip packages, due to the lack of effective prediction methods before the floor planning stage.
Innovation Solution
A method for analyzing register-transfer-level structures using a computing system with a knowledge base and logical congestion metric analysis engine to predict routing congestion by computing and comparing metric values, identifying congestion severity, and providing graphical indications of congestion issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If routing congestion is addressed during physical implementation, then routing issues can be resolved, but development time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by performing logical congestion metric analysis on RTL structures before floor planning and physical implementation. The system computes congestion-predicting metric values (such as fanout span depth, neighbor distribution, and logic depth) and compares them against thresholds to predict routing congestion issues in advance, allowing corrective actions to be taken during the design phase rather than during costly physical implementation.
2Reliability
If floorplan is changed to allocate more area for affected blocks, then routing congestion can be reduced, but design performance degrades and floorplan becomes sub-optimal
Solution Approach 1:
The patent implements feedback by providing designers with quantitative congestion predictions based on computed metric values. The system identifies specific RTL structures (such as multiplexers, logic cones, and nets) that are likely to cause routing congestion and provides feedback on their congestion severity. This enables designers to modify the HDL description or design architecture proactively, avoiding the need for sub-optimal floorplan changes and maintaining design performance while preventing routing congestion.
3Reliability
If HDL description is changed to resolve congestion, then routing issues can be fixed, but development time and cost increase
Solution Approach 1:
The patent applies preliminary action by analyzing RTL structures before physical implementation and identifying congestion-prone designs in advance. The logical congestion metric analysis engine computes metrics such as fanout span depth, neighbor distribution, and logic depth to predict which HDL descriptions will result in routing congestion. This allows designers to modify the HDL description during the design phase rather than after physical implementation has begun, significantly reducing development time and cost.
4Reliability
If design utilization is decreased to reduce congestion, then routing can be completed, but silicon area increases
Solution Approach 1:
The patent implements feedback by providing quantitative congestion predictions that enable designers to optimize their HDL descriptions before physical implementation. The system identifies specific structural patterns (such as wide-and-deep multiplexers, high fanout nets, and large logic cones) that cause congestion and provides feedback on their congestion severity. This allows designers to modify the design to achieve routing completion with optimal silicon area utilization, avoiding the need to unnecessarily decrease design utilization and increase area.
Data Source
AI summary
A logical congestion metric analysis engine predicts pre-placement routing congestion of integrated circuit designs. The engine uses a method employing new congestion-predicting metrics derived from structural register transfer level (RTL). The method compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. A logical congestion debug tool allows users to visualize and fix congestion issues.