RTL Memory Inference for Accurate CDC and RDC Verification

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Solution Overview

Problem

Conventional CDC and RDC verification tools inadequately address data integrity and performance issues due to treating memories as flip-flops, leading to missed bugs, noise from excessive violations, and performance overhead, as they fail to accurately analyze memory-specific sequential value propagations and metastability in semiconductor chip design.

Innovation Solution

The method involves inferring memory blocks in RTL representations of integrated circuits, designating input and output ports as start and end points, and performing domain crossing analysis to block qualifier signals and prevent metastable signals from propagating, thereby enhancing CDC and RDC verification accuracy and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional CDC and RDC verification tools treat memories as flip-flops, then the verification process is simpler, but the accuracy of detecting data integrity issues and metastability bugs deteriorates

Engineering Contradiction:

Improveverification process complexityVSAvoidbug detection accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The verification tool segments the analysis by distinguishing between memory blocks and regular flip-flops. Memory blocks are identified as special sequential elements with unique properties (bulk storage, port-based access), separating them from individual flip-flop analysis. This segmentation allows tailored verification approaches for each element type, improving bug detection accuracy without overwhelming complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention adds a new dimension to verification by introducing memory-specific analysis capabilities beyond traditional flip-flop modeling. Instead of treating all sequential elements uniformly in one dimension, the tool adds memory block as a distinct analytical dimension with specialized rules for detecting CDC and RDC issues specific to memory structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If conventional tools analyze all sequential elements including memories as flip-flops, then comprehensive coverage is achieved, but the number of false violations and noise increases

Engineering Contradiction:

Improveverification coverageVSAvoidfalse violations and noise

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The verification tool applies local quality by implementing memory-specific verification rules that differ from general flip-flop rules. Instead of uniform analysis, the tool tailors the verification approach to the local characteristics of memory blocks (such as their port structures and bulk storage behavior), reducing false violations while maintaining comprehensive coverage through specialized analysis.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The invention inverts the conventional approach by not treating memories as flip-flops, but rather treating flip-flops as individual elements and memories as distinct bulk storage blocks. This inversion allows the verification tool to apply appropriate analysis methods for each element type, eliminating the noise generated by misapplying flip-flop rules to memory structures.

Inventive Principle:

Principle #13The other way round (Inversion)

3Measurement precision

If conventional tools perform detailed analysis on all sequential elements, then thorough verification is achieved, but computational performance and resource usage deteriorate

Engineering Contradiction:

Improveverification thoroughnessVSAvoidverification performance

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The verification tool segments the computational workload by separating memory block analysis from individual flip-flop analysis. This segmentation allows the tool to apply more efficient analysis methods appropriate for each element type, maintaining thorough verification of CDC and RDC paths while reducing the overall computational burden through optimized processing of memory structures.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10878153B1Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference

Publication Date: 2020.12.29 SYNOPSYS INC

AI summary

Apparatuses and methods for performing domain crossing verification of a register transfer level (RTL) representation of an integrated circuit (IC) that includes a memory block are provided. One example method includes receiving an RTL representation of an IC; automatically inferring one or more memory blocks in the RTL representation of the IC; identifying one or more input ports and one or more output ports of the one or more memory blocks; designating the one or more input ports and the one or more output ports as one or more start points and one or more end points; and performing domain crossing analysis on the RTL representation.