RTL Signal Mapping for Gate-Level Debugging
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Solution Overview
Problem
Debugging complex circuit designs at the register transfer level is challenging due to logic optimization in gate-level netlists, which eliminates internal signals, making it difficult for emulators to accurately represent waveform data and hinder debugging at the RTL level.
Innovation Solution
A method that processes RTL netlists to produce non-optimized and optimized gate-level netlists, preserving all circuit signals, and generates additional waveform data to represent internal signals based on logical relationships, enabling debugging at the RTL level despite optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic optimization is applied in gate-level netlist synthesis, then resource usage is reduced and circuit efficiency is improved, but internal signals are eliminated making debugging at RTL level difficult
Solution Approach 1:
The system performs preliminary action by generating a mapping between RTL signals and gate-level signals before optimization occurs. This mapping is created during the synthesis phase, allowing the debugger to later correlate RTL-level internal signals with their gate-level counterparts even after optimization eliminates those internal signals from the optimized netlist.
Solution Approach 2:
The invention introduces an intermediary mapping data structure that connects RTL netlist signals to gate-level netlist signals. This intermediary allows the debugger to translate RTL-level debugging requests into gate-level signal references, bridging the gap between the optimized circuit and the original RTL design intent.
2Speed
If emulation is performed at gate level, then verification speed is improved, but loss of RTL-level signal information hinders debugging
Solution Approach 1:
The system creates a copy of the signal mapping relationship between RTL and gate-level netlists. This copied mapping information is stored and used by the debugger to reconstruct RTL-level signal behavior from gate-level emulation data, preserving RTL signal information without sacrificing gate-level emulation speed.
Solution Approach 2:
The mapping data structure serves as an intermediary that preserves RTL signal information while working with gate-level emulation data. It allows the debugger to access RTL-level signal names and relationships even though the actual emulation occurs at the optimized gate level, preventing information loss.
3Ease of operation
If internal signals are preserved in gate-level netlist, then RTL-level debugging is facilitated, but resource usage and circuit complexity increase
Solution Approach 1:
The invention extracts only the necessary mapping information between RTL and gate-level signals, rather than preserving all internal signals in the optimized netlist. By taking out just the essential signal correspondence data, it enables RTL-level debugging without adding the full complexity of preserving all internal RTL signals in the gate-level implementation.
Data Source
AI summary
A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.