RTZ Latch Feedback Path for High-Speed Decision Feedback Equalizers
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Solution Overview
Problem
High-speed decision feedback equalizers face challenges in reducing feedback delay to effectively mitigate intersymbol interference (ISI) as data rates increase, limiting their ability to operate efficiently in rapidly shrinking unit interval times.
Innovation Solution
The use of return to zero (RTZ) latches to slice incoming data streams into half-rate streams, allowing direct feedback to feedback taps without intervening logic, enabling low-delay decision feedback equalization with inherent parallel-to-serial conversion, ensuring real-time updates and correction of current data bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DFE techniques are used with master-slave latches, then data bits can be sampled and stored, but feedback delay increases as data rate increases, limiting DFE operation at high speeds
Solution Approach 1:
The patent divides the feedback path into two separate half-rate feedback paths, each handling alternating data bits (even and odd bits). This segmentation allows each path to operate at half the full data rate, reducing the feedback delay requirement for each individual path while maintaining full-rate operation through parallel processing.
Solution Approach 2:
The patent introduces a time-division multiplexing dimension by alternating between even and odd data bit streams. By processing these streams in separate half-rate cycles and combining them at the summation junction, the system effectively adds a temporal dimension to the feedback operation, allowing full-rate DFE functionality with reduced per-cycle delay requirements.
2Reliability
If feedback connections include intervening logic, then proper signal conditioning is achieved, but delay increases preventing proper DFE operation at high speeds
Solution Approach 1:
The patent extracts and removes unnecessary intervening logic from the feedback path by directly connecting the latch outputs to the summation junction. The RTZ latch design inherently provides the necessary signal conditioning through its reset behavior, eliminating the need for additional buffer logic or signal conditioning circuits that would increase delay.
Solution Approach 2:
The RTZ latch structure is designed to automatically provide the required signal characteristics for feedback operation. The latch self-regulates its output timing and level through its inherent reset-to-zero behavior, eliminating the need for external signal conditioning logic and reducing overall feedback loop delay.
3Productivity
If full-rate DFE operation is implemented, then bandwidth is maximized, but the unit interval shrinks making it difficult to complete DFE functions within the available time
Solution Approach 1:
The patent segments the full-rate data stream into two half-rate streams (even and odd bits), allowing the feedback computation to be performed at half the original rate. This segmentation effectively doubles the available time unit for each feedback operation while maintaining full-rate output through parallel stream processing.
Solution Approach 2:
The patent implements periodic alternating operation between even and odd data bit streams, where each stream is processed at half-rate in alternating cycles. This periodic time-division multiplexing allows the system to maintain full-rate throughput while reducing the time required for individual feedback computations.
Data Source
AI summary
A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE). An input data stream (DATA) is sliced into an even data stream and an odd data stream. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, half of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is then summed in current mode with the feedback data and converted to voltage prior to sampling of the currently received data bit.