Rutile Dielectric Layer Stack for Thin Memory Leakage Control
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Solution Overview
Problem
In highly integrated electronic devices, reducing the thickness of dielectric layers in memory devices leads to lower leakage current characteristics and operational reliability, necessitating a balance of high permittivity and low leakage current while maintaining a small thickness.
Innovation Solution
The use of a dielectric layer structure comprising a second dielectric layer with a rutile phase, flanked by first and third dielectric layers with higher energy bandgaps, and a second electrode with a rutile phase, formed through sequential deposition and heat treatment to achieve high permittivity and low leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the dielectric layer is reduced to increase degree of integration, then the device size is reduced, but the leakage current increases and operational reliability decreases
Solution Approach 1:
The patent employs a composite dielectric layer structure consisting of a first dielectric layer (e.g., TiO2 with rutile phase), a second dielectric layer (e.g., HfO2 with tetragonal or orthorhombic phase), and optionally a third dielectric layer. This composite structure combines materials with different properties: the TiO2 layer provides high permittivity (k≥80) while the HfO2 layer provides high energy bandgap (≥3.0 eV) for low leakage current. The synergistic combination allows achieving both high capacitance and low leakage in ultra-thin configurations (total thickness 5-20 nm), thus resolving the contradiction between device miniaturization and reliability maintenance.
Solution Approach 2:
The patent utilizes phase transitions and crystal structure transformations to optimize dielectric properties. Specifically, heat treatment processes transform the TiO2 layer from amorphous or anatase phase to rutile phase, which has higher permittivity. Similarly, the HfO2 layer is transformed from amorphous to crystalline phases (tetragonal or orthorhombic) with higher energy bandgap. These parameter changes in material phases enable the ultra-thin dielectric stack to simultaneously achieve high permittivity and low leakage current, maintaining reliability in miniaturized devices.
2Volume of moving object
If the thickness of the dielectric layer is reduced to increase degree of integration, then the device size is reduced, but the permittivity must be increased to maintain capacitance
Solution Approach 1:
The patent employs a composite dielectric layer structure consisting of a first dielectric layer (e.g., TiO2 with rutile phase), a second dielectric layer (e.g., HfO2 with tetragonal or orthorhombic phase), and optionally a third dielectric layer. This composite structure combines materials with different properties: the TiO2 layer provides high permittivity (k≥80) while the HfO2 layer provides high energy bandgap (≥3.0 eV) for low leakage current. The synergistic combination allows achieving both high capacitance and low leakage in ultra-thin configurations (total thickness 5-20 nm), thus resolving the contradiction between device miniaturization and reliability maintenance.
Solution Approach 2:
The patent utilizes phase transitions and crystal structure transformations to optimize dielectric properties. Specifically, heat treatment processes transform the TiO2 layer from amorphous or anatase phase to rutile phase, which has higher permittivity. Similarly, the HfO2 layer is transformed from amorphous to crystalline phases (tetragonal or orthorhombic) with higher energy bandgap. These parameter changes in material phases enable the ultra-thin dielectric stack to simultaneously achieve high permittivity and low leakage current, maintaining reliability in miniaturized devices.
3Device complexity
If a single dielectric layer is used to simplify the structure, then the device complexity is reduced, but the leakage current cannot be sufficiently controlled
Solution Approach 1:
The patent employs a composite dielectric layer structure consisting of a first dielectric layer (e.g., TiO2 with rutile phase), a second dielectric layer (e.g., HfO2 with tetragonal or orthorhombic phase), and optionally a third dielectric layer. This composite structure combines materials with different properties: the TiO2 layer provides high permittivity (k≥80) while the HfO2 layer provides high energy bandgap (≥3.0 eV) for low leakage current. The synergistic combination allows achieving both high capacitance and low leakage in ultra-thin configurations (total thickness 5-20 nm), thus resolving the contradiction between device miniaturization and reliability maintenance.
Solution Approach 2:
The patent applies different material compositions and phases to different layers within the dielectric stack. The first layer (TiO2 rutile) is optimized for high permittivity, the second layer (HfO2 crystalline) is optimized for high energy bandgap and low leakage, and the third layer (if present) provides additional protection or interface engineering. This local optimization of material properties in each layer enables the structure to simultaneously achieve high capacitance and low leakage current, overcoming the limitations of single-material dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high dielectric constant and reduces leakage current, ensuring stable operation and increased reliability in highly integrated semiconductor devices.
Implementation Method 1
crystallizing the second dielectric layer into a rutile phase by heat treating of the first electrode, the first dielectric layer, the second dielectric layer, and the third electrode
Implementation Method 2
crystallizing the second dielectric layer into a rutile phase by heat treating of the first electrode, the first dielectric layer, the second dielectric layer, and the third electrode
Implementation Method 3
sequentially forming a first dielectric layer and a second dielectric layer on a first electrode
Implementation Method 4
sequentially forming a first dielectric layer and a second dielectric layer on a first electrode
Data Source
AI summary
An electronic device and a manufacturing method including a dielectric layer according to at least some embodiments are disclosed. The electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a first dielectric layer between the first electrode and the second electrode, a second dielectric layer having a rutile phase, a third dielectric layer between the first dielectric layer and the second electrode, and a third dielectric layer between the second dielectric layer and the second electrode and including a material having a higher energy bandgap than a material included in the second dielectric layer.