Sacrificial Hard Mask Patterning for Semiconductor Pillar Formation
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Solution Overview
Problem
Conventional semiconductor integrated circuit fabrication methods are complex and costly due to the difficulty in forming small patterns, particularly pillar patterns, which require multiple steps and processes like CMP and additional photo processes to achieve small design rules.
Innovation Solution
A method involving the formation of a hard mask layer and sacrificial hard mask layers, with a high molecular organic material layer used for planarization, allowing for the creation of line-and-space patterns in multiple directions without the need for CMP, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods use oxidation layer filling and CMP process to form pillar patterns, then small design rules can be achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent extracts and removes the CMP process and oxidation layer filling steps from the conventional fabrication sequence. Instead of using oxidation layers that require CMP planarization, the invention directly forms pillar patterns through selective etching of sacrificial layers, eliminating the need for CMP and reducing process complexity while maintaining small design rule capability
Solution Approach 2:
The patent segments the patterning process into multiple directional steps (first direction line-and-space patterning, then second direction patterning) to form pillar patterns. This segmentation allows achieving small design rules through sequential simpler steps rather than requiring complex single-step patterning, thereby reducing overall process complexity
2Manufacturing precision
If conventional methods use multiple patterning steps with oxidation layer filling, then pillar patterns with small design rules are formed, but additional photo processes and cleaning steps are required
Solution Approach 1:
The patent merges the patterning of multiple layers into a unified process flow. By forming line-and-space patterns in the first direction, then patterning in the second direction to create matrix-shaped sacrificial patterns, the invention achieves precise pillar patterns without requiring separate oxidation layer filling and cleaning steps, thereby improving fabrication efficiency
Solution Approach 2:
The patent performs preliminary patterning actions by first creating line-and-space patterns in one direction, then using these as a basis for subsequent patterning in another direction. This preliminary structuring enables precise pillar formation without requiring additional photo processes or cleaning steps that would reduce productivity
3Reliability
If conventional methods use I-Line photo process and liftoff to prevent alignment key liftoff, then alignment is maintained, but process steps and cost increase
Solution Approach 1:
The patent extracts and eliminates the I-Line photo process and liftoff steps from the conventional alignment protection sequence. By using sacrificial layers that can be selectively removed through etching processes, the invention maintains alignment key stability without requiring additional photo processes, thereby reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of accurate patterns with small design rules using the line-and-space pattern twice, increasing productivity and reducing fabrication costs by eliminating the need for additional planarization and cleaning processes.
Implementation Method 1
planarizing upper surface of the line sacrificial hard mask layer pattern by coating a high molecular organic material layer on the line sacrificial hard mask layer pattern
Implementation Method 2
patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in the form of a line-and-space pattern such that it is in a second direction, not parallel with the first direction, forming a matrix sacrificial hard mask layer pattern arranged in a matrix shape by removing the high molecular organic material pattern
Data Source
AI summary
Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.