Sacrificial Layer Interconnect for Low-k Dielectric Protection

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Solution Overview

Problem

Low-k dielectric materials used in semiconductor devices are susceptible to damage during etching processes, leading to issues such as higher leakage currents, lower breakdown voltages, and changes in dielectric constant, which affect the yield, performance, and reliability of integrated circuit devices.

Innovation Solution

A method for forming interconnect structures that involves depositing a sacrificial layer and a dielectric hard mask layer, patterning and etching to create features, depositing a metal layer, removing the sacrificial layer, and filling recesses with a low-k dielectric material, which encapsulates metal bodies and forms air gaps, eliminating the need for etch stop or anti-reflective coating layers and reducing damage to low-k dielectric materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low-k dielectric materials are used to reduce RC delay, then circuit performance is improved, but the dielectric materials become susceptible to damage during etching processes

Engineering Contradiction:
Improvecircuit speedVSAvoiddielectric material integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A sacrificial layer is deposited over the low-k dielectric material before subsequent etching operations. This preliminary protective layer prevents direct exposure of the low-k material to damaging etchants, thereby maintaining dielectric integrity while enabling the use of low-k materials for high-speed circuits

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional etching processes are used on low-k dielectric materials, then manufacturing simplicity is maintained, but damage occurs leading to higher leakage currents and lower breakdown voltages

Engineering Contradiction:
Improveetching process simplicityVSAvoidetching damage to dielectric
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The sacrificial layer acts as an intermediary protective barrier between the etching process and the low-k dielectric material. This intermediate layer absorbs the harmful effects of etchants, allowing conventional etching processes to proceed without directly damaging the sensitive dielectric material

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If etch stop or anti-reflective coating layers are used to protect low-k dielectric materials, then dielectric damage is reduced, but process complexity and cost increase

Engineering Contradiction:
Improvedielectric material protectionVSAvoidnumber of process layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layer serves multiple functions: it protects the low-k dielectric during etching, acts as an etch stop layer, and eliminates the need for separate anti-reflective coating layers. This multi-functional approach reduces overall process complexity while maintaining dielectric protection

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces damage to low-k dielectric materials during etching, improves the yield and performance of integrated circuit devices, and eliminates the need for costly etch stop or anti-reflective coating layers, making the process more cost-effective.

Implementation Method 1

filling recesses with a low-k dielectric material, which encapsulates metal bodies and forms air gaps

Methodology Applied
Scientific EffectEncapsulation:

Data Source

PatentUS8728936B1Copper etching integration scheme
Publication Date: 2014.05.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8728936B1 patent drawing
  • US8728936B1 patent drawing
  • US8728936B1 patent drawing

AI summary

The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage.