Sacrificial Layer Protects Dielectric During Interconnect Polishing
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Solution Overview
Problem
The increasing density and shrinking size of integrated circuits (ICs) lead to variations in topography, compromising the reliability of interconnects and dielectric layers, which can result in processing window issues and degradation of hydrophobic properties during polishing, affecting the integrity of the ICs.
Innovation Solution
A sacrificial layer is used to protect the dielectric layer during polishing and processing, maintaining the hydrophobic properties and achieving a planar surface by removing the sacrificial layer through a non-etching decomposing anneal, ensuring the dielectric layer remains intact and defect-free.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing is performed on the dielectric layer to achieve planarity, then the surface flatness is improved, but the hydrophobic properties of the dielectric layer are degraded
Solution Approach 1:
A sacrificial layer is introduced as an intermediary protective layer between the polishing interface and the dielectric layer. This sacrificial layer absorbs the mechanical and chemical effects of polishing, preventing direct contact between the polishing tools and the dielectric layer, thereby preserving the hydrophobic properties while achieving the desired surface flatness.
Solution Approach 2:
The sacrificial layer is applied to the dielectric layer before the polishing process. This preliminary action prepares the surface by providing a protective barrier that will be removed after polishing, ensuring that the dielectric layer's hydrophobic properties are not compromised during the planarization process.
2Productivity
If increased density features are added to shrink IC size, then the functionality is improved, but the topography variation increases compromising reliability
Solution Approach 1:
The planarization process is segmented into multiple controlled steps: applying sacrificial layer, polishing, and removing sacrificial layer. This segmentation allows for precise control of each step, enabling the process to handle high-density features with varying topographies while maintaining reliability and processing window.
Solution Approach 2:
The use of sacrificial layer changes the physical parameters of the surface during polishing, creating a temporary protective interface that allows polishing parameters to be optimized for flatness without negatively impacting the dielectric layer's properties. This parameter change enables reliable processing of high-density interconnect structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of ICs by maintaining the hydrophobic properties and defect-free surface of the dielectric layer, improving the integrity and performance of interconnects by preventing damage during processing.
Implementation Method 1
The sacrificial layer protects the dielectric layer during polishing of the conductive material
Implementation Method 2
The conductive material is polished to produce a top surface of the conductive material that is substantially planar
Implementation Method 3
The sacrificial layer is removed through a non-etching decomposing anneal
Data Source
AI summary
A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.