Sacrificial Layer Singulation for Optoelectronic Semiconductor Chips

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Solution Overview

Problem

Current methods for producing optoelectronic semiconductor chips, such as LED chips, face challenges in efficiently singulating chips from a wafer composite while maintaining chip geometry and minimizing damage to the semiconductor layer sequence.

Innovation Solution

A method involving the growth of a semiconductor layer sequence on a substrate, attachment of a carrier substrate, deposition of a sacrificial layer, and division using a singulation stream, particularly laser radiation or plasma, where the sacrificial layer acts as a cutting mask to create non-linear chip geometries and allows for continuous beam guidance without damaging the semiconductor layer sequence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If a sacrificial layer is deposited and structured to form singulation lanes, then non-linear chip geometries can be achieved and continuous beam guidance is enabled, but the device complexity and manufacturing steps increase

Engineering Contradiction:
Improvechip geometryVSAvoidprocess complexity
Core Design Contradiction:
ShapeVSDevice complexity

Solution Approach 1:

A sacrificial layer is deposited onto the carrier substrate before the singulation process. This layer is then structured to form singulation lanes that guide the singulation beam. The sacrificial layer is removed in areas where singulation is required, creating defined paths for the beam while protecting areas where chips should remain intact. This preliminary structuring enables complex non-linear chip geometries to be achieved through continuous beam guidance without requiring mechanical intervention or multiple processing steps.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If mechanical dicing or conventional laser cutting is used for singulation, then the process is simple, but adjacent chips are damaged or contaminated by flying chips and molten material

Engineering Contradiction:
Improvesingulation simplicityVSAvoidchip damage and contamination
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

A sacrificial layer is introduced as an intermediary between the singulation beam and the chip structures. This layer absorbs the beam energy in designated singulation lanes, converting it to heat that separates the chips along predefined paths. The sacrificial layer acts as a buffer that confines the thermal and mechanical effects of singulation to specific regions, preventing flying chips and molten material from contaminating adjacent chips. The layer is subsequently removed, leaving clean singulation edges without damaging the chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the singulation beam is continuously guided over the entire carrier substrate, then throughput is improved, but the semiconductor layer sequence may be damaged without protective masking

Engineering Contradiction:
Improvesingulation throughputVSAvoidsemiconductor layer integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The sacrificial layer is selectively structured to have different properties in different regions of the carrier substrate. In singulation lane areas, the layer is removed or thinned to allow beam penetration and energy absorption. In chip areas, the layer remains intact to protect the semiconductor layer sequence from beam damage. This local differentiation enables the singulation beam to be continuously guided over the entire substrate without damaging the chips, as the protective sacrificial layer is present only where needed while allowing efficient singulation where required.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient separation of semiconductor chips with non-rectangular shapes, high throughput, and low adjacent chip loss, while protecting the semiconductor layer sequence from damage during the singulation process.

Implementation Method 1

the dividing takes place via laser ablation, laser evaporation, laser melting or so-called stealth dicing and alternatively or additionally via a plasma process such as plasma cutting or reactive ion etching

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

a plasma process such as plasma cutting or reactive ion etching, in short RIE

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 3

the sacrificial layer adjacent to the separation lanes is not transmissive to the separation stream

Methodology Applied
Scientific EffectLaser reflection: Reflection

Data Source

PatentUS11289620B2Method of producing optoelectronic semiconductor chips and optoelectronic semiconductor chip
Publication Date: 2022.03.29 AMS OSRAM INT GMBH
  • US11289620B2 patent drawing
  • US11289620B2 patent drawing
  • US11289620B2 patent drawing

AI summary

A method for producing optoelectronic semiconductor chips and an optoelectronic semiconductor chip are disclosed. In an embodiment a method includes growing a semiconductor layer sequence with an active, attaching a carrier substrate, depositing a sacrificial layer on an outer side of the carrier substrate and/or of the growth substrate, structuring the sacrificial layer so that singulation lanes are formed and dividing the carrier substrate and/or the growth substrate along the singulation lanes by a singulation stream including a laser radiation or a plasma, wherein the sacrificial layer adjacent to the singulation lanes is not transmissive to the singulation stream, and wherein the singulation stream is passed both through the singulation lanes and over the sacrificial layer.