Alternating Sacrificial Layers for Stable 2D Nanoribbon Etch
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Solution Overview
Problem
The scaling of semiconductor devices to sub-10 nanometer nodes is hindered by the susceptibility of thin, layered transition metal dichalcogenide (TMD) channels to mechanical damage during fabrication due to lack of support, leading to defects in transistor formation.
Innovation Solution
The use of alternating sacrificial layers that are etch selective to each other provides constant mechanical support to TMD channels, allowing for their safe handling and integration into 2D nanoribbon transistor architectures by selectively removing and replacing these layers with gate stack components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TMD channels are scaled to sub-10 nanometer nodes, then device density and capacity are improved, but the channels become susceptible to mechanical damage due to lack of support
Solution Approach 1:
The patent introduces sacrificial layers as intermediary structures that provide mechanical support to TMD channels during fabrication. These layers act as temporary mediators between the fragile TMD channels and the fabrication process, preventing mechanical damage while enabling continued scaling to sub-10 nanometer nodes.
Solution Approach 2:
The sacrificial layers are deposited beforehand to provide mechanical support before the TMD channels are fully formed and before any potentially damaging fabrication steps occur. This preliminary action ensures the channels have the necessary structural support during subsequent processing operations.
2Reliability
If sacrificial layers are used to support TMD channels, then mechanical integrity is improved, but fabrication process complexity increases due to multiple etching steps
Solution Approach 1:
The patent divides the sacrificial layer structure into multiple segments with different etch selectivities. Each segment can be removed independently through selective etching processes, allowing for staged removal that simplifies the overall fabrication process while maintaining mechanical support during critical stages.
Solution Approach 2:
The patent varies the etch selectivity parameter of different sacrificial layer materials to enable selective removal. By choosing materials with different etch rates and selectivities, the fabrication process can remove sacrificial layers in a controlled sequence without requiring overly complex processing steps.
3Ease of manufacture
If alternating sacrificial layers with different etch selectivities are used, then selective removal is enabled for gate stack formation, but material selection and process optimization become more difficult
Solution Approach 1:
The patent applies different material compositions to different sacrificial layer segments based on their specific functional requirements. Each segment is optimized locally for its particular role in the fabrication process, with material selection tailored to the specific etching conditions and mechanical support needs of that region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the integrity of TMD channels throughout the fabrication process, preventing damage from capillary forces and enabling the formation of functional transistors with aggressive scaling capabilities.
Implementation Method 1
a first sacrificial layer and a second sacrificial layer alternating and around the plurality of semiconductor channels, wherein the first sacrificial layer is etch selective to the second sacrificial layer
Implementation Method 2
provides constant mechanical support to TMD channels, allowing for their safe handling and integration into 2D nanoribbon transistor architectures
Data Source
AI summary
Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.