Saddle Fin Gate Structure for Transistor Controllability
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving adequate threshold voltage and refresh characteristics due to short channel effects and increased junction leakage current, particularly as transistor integration increases, leading to degraded controllability and poor transistor characteristics.
Innovation Solution
A semiconductor device with a saddle fin shaped gate is developed, featuring grooves in the gate forming areas and isolation structure that expose front and rear surfaces, with lower portions of the grooves being wider than upper portions, and an impurity ion implantation layer is formed to enhance gate controllability and reduce drain-induced barrier lowering and swing properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar channel structure designs are used, then manufacturing is simple, but threshold voltage control is inadequate due to short channel effects
Solution Approach 1:
The patent transitions from a conventional planar (2D) channel structure to a three-dimensional fin channel structure. The fin channel protrudes vertically from the substrate, creating additional surface area for the gate to control the channel. This dimensional change allows the gate to effectively control the channel even as dimensions scale down, addressing the short channel effect problem while maintaining manufacturing feasibility through established etching and deposition processes.
Solution Approach 2:
The isolation structure is selectively etched to create exposed front and rear surfaces of the fin channel, segmenting the gate control region. This segmentation allows the gate to control the channel from multiple surfaces (front, rear, and top), improving threshold voltage control through enhanced electric field distribution across the channel region.
2Productivity
If cell size is reduced to increase integration, then device density increases, but gate controllability deteriorates and DIBL properties are degraded
Solution Approach 1:
By creating a vertical fin structure, the patent increases the effective channel width without increasing the lateral footprint. The gate controls the channel from the top, front, and rear surfaces, providing superior controllability even as the cell size is reduced for higher integration density.
Solution Approach 2:
The structure combines the fin channel protruding from the substrate with the isolation structure, creating a composite architecture. The selective etching of the isolation structure exposes multiple surfaces of the fin channel, allowing the gate to control the channel from multiple angles and improving gate controllability in highly integrated devices.
3Area of moving object
If fin channel structure is used, then channel area increases and current drivability improves, but manufacturing complexity increases
Solution Approach 1:
The isolation structure is selectively etched to create exposed front and rear surfaces of the fin channel, segmenting the gate control region. This segmentation allows the gate to control the channel from multiple surfaces (front, rear, and top), improving threshold voltage control through enhanced electric field distribution across the channel region.
Solution Approach 2:
The fin channel structure serves multiple functions: it increases the channel area for improved current drivability, provides vertical separation for device isolation, and creates multiple exposed surfaces for enhanced gate control. This multi-functionality justifies the additional manufacturing steps by delivering multiple performance benefits simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves transistor characteristics by increasing the channel area, enhancing current drivability, and reducing short channel effects, thereby improving the controllability and performance of transistors in high-integration semiconductor devices.
Implementation Method 1
an impurity ion implantation layer is formed in lower portions of the isolation structure which adjoin the exposed front and rear surfaces of the gate forming areas
Data Source
AI summary
A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.