SADP Patterning for Semiconductor Array and Peripheral Fidelity
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Solution Overview
Problem
The semiconductor manufacturing process faces challenges in accurately transferring patterns of dense designs to substrates due to shrinking feature dimensions and increased complexity, leading to difficulties in fidelity and manufacturability, especially when dealing with multiple pattern types in a single design layer.
Innovation Solution
A patterning method involving self-aligned double patterning (SADP) processes with multiple patterned layers and etching steps to form ideal array and peripheral circuit features, using a hard mask layer and pattern transferring layers to enhance pattern fidelity and manufacturability, allowing for the formation of dense patterns with simplified process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography-etching process is used, then the process is simple, but the pattern transfer fidelity deteriorates due to shrinking feature dimensions and dense patterns
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps including forming first and second patterned layers, performing first and second SADP processes, and selective etching operations. Each step creates intermediate patterns that are progressively refined to achieve the final high-fidelity pattern transfer, breaking down the complex task into manageable segments that maintain precision at each stage
Solution Approach 2:
The patent introduces vertical layering with multiple patterned layers formed at different heights on the substrate. The first patterned layer undergoes SADP to create sidewall spacers, then the second patterned layer is formed and processed. This multi-dimensional approach allows complex 2D patterns to be transferred with high fidelity by utilizing the third dimension (vertical stacking) to guide the patterning process
2Productivity
If feature dimensions are shrunk for higher integration, then device integration increases, but manufacturing difficulty increases due to pattern transfer challenges
Solution Approach 1:
The patent performs preliminary patterning actions by forming the first patterned layer and executing the first SADP process to create precisely defined intermediate patterns before forming the second patterned layer. These preliminary patterns serve as templates that guide subsequent processing steps, ensuring that even as feature dimensions shrink, the manufacturing process maintains control and precision through pre-established pattern frameworks
Solution Approach 2:
The patent introduces intermediate patterned layers and spacer structures that act as mediators between the photomask and the final target pattern. The first and second patterned layers, along with SADP-generated sidewall spacers, serve as intermediary elements that facilitate accurate pattern transfer at reduced dimensions, making the manufacturing process more manageable despite smaller feature sizes
3Adaptability or versatility
If multiple dense patterns are incorporated in a same design layer, then circuit functionality improves, but pattern transfer accuracy deteriorates
Solution Approach 1:
The patent applies different processing treatments to different regions of the substrate through the multi-layer approach. The first patterned layer and first SADP process create local patterns in specific areas, while the second patterned layer and second SADP process address other regions. This localized quality control allows multiple dense patterns with different requirements to be accurately transferred within the same design layer by tailoring the patterning approach to each region's specific needs
Data Source
AI summary
A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.