Same-Duty-Cycle Clock Control for Scan Chain Timing Exceptions
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Solution Overview
Problem
The challenge of managing power consumption and handling timing exceptions during at-speed capture in integrated circuits, particularly in large silicon chips with complex logic levels, leads to issues such as excessive heat generation, voltage drop, and reduced fault coverage due to multi-cycle and false paths.
Innovation Solution
A control circuit and integrated circuit design that generates multiple clock signals with the same duty cycle to manage power consumption by independently controlling clock and scan enable signals at endpoint flip-flops, using hardware masking and clock gating to mitigate power consumption and ensure comprehensive test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If at-speed capture is performed on large silicon chips with complex logic levels, then test coverage and fault detection capability are improved, but power consumption increases excessively leading to heat dissipation and voltage drop issues
Solution Approach 1:
The scan chain is divided into multiple segments with different clock signal assignments. Endpoint flip-flops are segmented into first endpoint flip-flops receiving first clock signals and second endpoint flip-flops receiving second clock signals. This segmentation allows selective clock gating to reduce power consumption while maintaining fault coverage in critical segments.
Solution Approach 2:
Clock signals are applied periodically to different scan chain segments based on their testing needs. The first clock signal is applied to first endpoint flip-flops and the second clock signal to second endpoint flip-flops during different time periods, enabling power reduction by activating only the necessary portions of the scan chain at any given time.
2Device complexity
If timing exceptions are handled by conventional ATPG tools ignoring SDC files, then test pattern generation is simpler, but timing constraints are violated leading to reduced effective test coverage
Solution Approach 1:
A control circuit acts as an intermediary between the ATPG tool and the scan chain, bridging the gap by translating high-level test patterns into clock-gated control signals. The control circuit receives control signals from the ATPG tool and generates appropriate first and second clock signals to endpoint flip-flops, ensuring timing constraints are met without complicating the ATPG tool itself.
3Device complexity
If uniform clock signals are applied to all endpoint flip-flops, then circuit design is simpler, but power consumption increases and timing exception handling becomes difficult
Solution Approach 1:
Different clock signal characteristics are applied to different portions of the scan chain based on local requirements. First endpoint flip-flops receive first clock signals while second endpoint flip-flops receive second clock signals, allowing each segment to be optimized for its specific timing and power requirements rather than using a uniform approach.
Solution Approach 2:
The clock signal distribution is made dynamic rather than static. The control circuit dynamically generates and applies different clock signals to different endpoint flip-flops based on testing requirements and timing exceptions, enabling flexible power management and timing constraint satisfaction during the testing process.
Data Source
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AI summary
According to an embodiment, a method for testing a scan chain (102) is provided. The method includes receiving a first clock signal (OCC_CLK) and a first scan enable signal (SCAN_EN_AB) and generating a second (CLK_A) and third clock signal (CLK_B) based on the first clock signal (OCC_CLK) and the first scan enable signal (SCAN_EN_AB). The third clock signal (CLK_B) is delayed by a clock pulse from the second clock signal (CLK_A). The first (OCC_CLK), second (CLK_A), and third (CLK_N) clock signal have the same duty cycle. The method further includes providing the second clock signal (CLK_A) and the second scan enable signal (SCAN_EN_A) to, respectively, a clock terminal and scan enable input of a first scan flip-flop (104) of the scan chain (102). The method further includes providing the third clock signal (CLK_B) and a third scan enable signal (SCAN_EN_B) to, respectively, a clock terminal and a scan enable input of a last scan flip-flop (106) of the scan chain (102).