Same-Sign Floating-Point Adders for Lower-Power Multi-Operand Summation

Solution Overview

Problem

In the design of hardware for processing units, there is a trade-off between power consumption, processing performance, and size (semiconductor area), and existing adder circuits do not efficiently address this balance, especially when adding multiple floating-point numbers.

Innovation Solution

The method involves identifying at least two floating-point numbers with the same sign from a set of numbers to be added, and using same-sign floating-point adders to perform the additions, thereby reducing the complexity and resources required compared to mixed-sign adders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If mixed-sign floating-point adders are used to add multiple floating-point numbers, then the addition can handle both positive and negative numbers, but the circuit complexity and silicon area increase

Engineering Contradiction:

Improveability to handle both positive and negative numbersVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the addition process into two distinct stages: first, same-sign additions are performed using simplified adders, and second, the results are combined using a single mixed-sign addition. This segmentation allows most additions to use simpler circuitry while maintaining the ability to handle both positive and negative numbers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts and handles the sign management aspect separately from the magnitude addition. By identifying numbers with the same sign and grouping them together, the complex sign handling logic is removed from the main addition path, leaving only simple magnitude addition for the same-sign groups.

Inventive Principle:

Principle #2Taking out (Extraction)

2Adaptability or versatility

If mixed-sign floating-point adders are used to add multiple floating-point numbers, then the addition can handle both positive and negative numbers, but the power consumption increases

Engineering Contradiction:

Improveability to handle both positive and negative numbersVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the addition process into two distinct stages: first, same-sign additions are performed using simplified adders, and second, the results are combined using a single mixed-sign addition. This segmentation allows most additions to use simpler circuitry while maintaining the ability to handle both positive and negative numbers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts and handles the sign management aspect separately from the magnitude addition. By identifying numbers with the same sign and grouping them together, the complex sign handling logic is removed from the main addition path, leaving only simple magnitude addition for the same-sign groups.

Inventive Principle:

Principle #2Taking out (Extraction)

3Area of stationary object

If same-sign floating-point adders are used without circuitry for different signs, then the silicon area is reduced, but the adder cannot directly add numbers with different signs

Engineering Contradiction:

Improvesilicon areaVSAvoidability to add numbers with different signs

Core Design Contradiction:

Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent segments the addition process into two distinct stages: first, same-sign additions are performed using simplified adders, and second, the results are combined using a single mixed-sign addition. This segmentation allows most additions to use simpler circuitry while maintaining the ability to handle both positive and negative numbers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary grouping of numbers by sign before the addition process. By pre-identifying and grouping numbers with the same sign, the simplified same-sign adders can be used without needing to handle sign changes during the addition operation itself.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12265797B2Apparatus and method for processing floating-point numbers

Publication Date: 2025.04.01 IMAGINATION TECH LTD

AI summary

Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.