Sample and Hold Circuit Temperature Compensation
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Solution Overview
Problem
Current sample and hold circuits face challenges in maintaining temperature stability during the hold phase, leading to potential drift in output current due to temperature variations.
Innovation Solution
The proposed sample and hold circuit incorporates a transistor arrangement with a control MOSFET and cascaded cells, where the control MOSFET has a negative temperature coefficient and the cascaded cells have a positive temperature coefficient, forming a closed-loop that compensates for temperature changes, ensuring stable output current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional sample and hold circuit is used, then the circuit can sample and hold current, but the output current drifts due to temperature variations during the hold phase
Solution Approach 1:
The patent changes the temperature coefficient parameter of the control MOSFET by selecting a device with a negative temperature coefficient. This parameter change allows the MOSFET's current characteristics to compensate for temperature-induced drift in the output current, thereby improving output stability during the hold phase
Solution Approach 2:
The patent implements a feedback mechanism where the control MOSFET's drain current is fed back to its gate through a resistive divider network. This feedback loop automatically adjusts the gate voltage in response to temperature changes, stabilizing the output current by counteracting temperature-induced variations
2Reliability
If the control MOSFET operates with negative temperature coefficient, then temperature compensation is achieved, but the circuit complexity increases due to additional components
Solution Approach 1:
The patent merges the temperature compensation function with the existing control MOSFET structure by utilizing its negative temperature coefficient characteristic. The feedback network is integrated into the MOSFET's gate control path, combining multiple functions (current control, temperature compensation, and stability regulation) into a unified circuit architecture rather than adding separate compensation circuits
Solution Approach 2:
The control MOSFET serves itself by utilizing its inherent negative temperature coefficient to automatically compensate for temperature drift. The feedback mechanism leverages the MOSFET's own electrical characteristics and thermal behavior, allowing the device to self-regulate its output current without requiring external temperature sensors or complex compensation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains a stable output current during temperature variations, as the positive thermal coefficient of the cascaded cells compensates for the negative thermal coefficient of the control MOSFET, resulting in negligible temperature sensitivity during the hold phase.
Implementation Method 1
the control MOSFET has a negative temperature coefficient thereby acting to increase the current at the output node for a given voltage at the capacitor with increasing temperature
Implementation Method 2
the one or more cascaded cells have a positive temperature coefficient thereby acting to decrease the current at the output node for a given voltage at the capacitor with increasing temperature
Data Source
AI summary
A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.