Sampled-Data Receiver Chopper Layout for Low-Alias Baseband Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wireless communication devices face challenges with flicker noise and voltage offset in RFFE circuitry, particularly in direct-conversion scenarios, which are exacerbated by chopper stabilization and result in additional noise interference.
Innovation Solution
The implementation of a receiver circuitry that includes chopper circuits, AC-coupling circuits, and clock dividers to reduce flicker noise and voltage offset, while avoiding alias components, by adjusting chopper frequencies and using AC-coupling to select common-mode levels and reduce signal loss at DC frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If chopper stabilization is employed to overcome flicker noise and voltage offset, then flicker noise and voltage offset are reduced, but additional noise is introduced due to chopper sampling operations
Solution Approach 1:
The baseband chain is divided into multiple discrete-time processing stages with separate sampling circuits and chopper circuits operating at different frequencies. This segmentation allows each stage to be optimized independently, reducing the propagation of noise while maintaining the benefits of chopper stabilization at each stage.
Solution Approach 2:
The patent employs multiple chopper frequencies (first chopper frequency and second chopper frequency) that are different from each other and from the sampling frequency. By changing the frequency parameters of the chopper circuits, the aliasing of chopper noise into the signal band is minimized, thereby reducing the additional noise introduced by chopper sampling operations.
2Use of energy by moving object
If discrete-time circuits are used to reduce power consumption and increase linearity, then power consumption is reduced and linearity is improved, but flicker noise and voltage offset from buffers or amplifiers are introduced
Solution Approach 1:
Chopper stabilization is applied at the input stage of each amplifier or buffer in the discrete-time baseband chain to preemptively reduce flicker noise and voltage offset before they can be amplified or propagated. This preliminary action prevents the harmful factors from affecting subsequent stages while maintaining the power efficiency of discrete-time circuits.
Solution Approach 2:
Chopper circuits are introduced as intermediary elements between sampling circuits and amplifiers/buffers. These chopper circuits modulate the signal to shift flicker noise and voltage offset to higher frequencies where they can be filtered out, thereby mediating the harmful effects while allowing the discrete-time circuits to operate efficiently.
3Measurement precision
If chopper frequency is increased to reduce aliasing, then alias components are reduced, but noise from chopper sampling may be amplified
Solution Approach 1:
Multiple chopper circuits operate at periodic frequencies that are specifically chosen to be different from the sampling frequency and from each other. This periodic action with varied frequencies creates a noise spectrum that is spread out and less likely to alias into the signal band, reducing both alias components and the amplification of chopper sampling noise.
Solution Approach 2:
The patent uses asymmetric frequency relationships where the first chopper frequency and second chopper frequency are deliberately made different and neither is an integer multiple of the sampling frequency. This asymmetric frequency planning prevents coherent aliasing and distributes noise energy across different frequency bands, reducing the overall impact of chopper sampling noise.
Data Source
AI summary
Embodiments herein provide various apparatuses and techniques to reduce flicker noise and voltage offset from the buffers and/or amplifiers while avoiding additional alias components in a sampled-data receiver with chopper stabilization. Additionally, a direct-conversion baseband chain may be improved by disposing alternating current (AC) coupling circuits between chopper circuits in the transmitter or receiver chain to enable selection of a distinct common-mode level at each stage of the direct-conversion chain, while reducing or eliminating signal loss at direct current (DC) frequencies.