Sampling Phase Interpolator With Feedback for Phase Accuracy
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Solution Overview
Problem
Phase interpolators in CDR circuits suffer from non-linearity and integral nonlinearity mismatch due to semiconductor manufacturing variations, affecting the quality of generated data.
Innovation Solution
A phase interpolator design comprising a phase detector, filter, and oscillator that adjusts clock signal phases using a detection result filtered by a low-pass filter and controlled by a voltage- or current-controlled oscillator, mitigating variations from PVT effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional phase interpolators are used in CDR circuits, then the circuit achieves high integration and low power consumption, but non-linearity and integral nonlinearity mismatch occur due to semiconductor manufacturing variations, affecting data quality
Solution Approach 1:
The patent implements a feedback mechanism where a phase detector continuously monitors the phase difference between the output clock signal and a reference clock signal. The detected phase error is fed back through a loop filter to adjust the oscillator frequency, creating a closed-loop system that automatically compensates for phase inaccuracies caused by manufacturing variations, thereby improving both data quality and phase accuracy
Solution Approach 2:
The patent replaces traditional mechanical or fixed-phase interpolation methods with a digitally controlled phase-locked loop system. Instead of relying on fixed hardware phase shifters that are sensitive to manufacturing variations, the system uses digital phase detection and feedback control to dynamically adjust and maintain accurate phase relationships, substituting rigid mechanical approaches with adaptive electronic control
2Adaptability or versatility
If multiple phase interpolators are used to cover different phase ranges, then the phase coverage is improved, but integral nonlinearity mismatch increases due to semiconductor process variations across different components
Solution Approach 1:
The patent creates a universal phase control system where a single phase-locked loop architecture can generate multiple phase-shifted clock signals. The system uses one oscillator and phase detector that can produce N different phase outputs by controlling the oscillator frequency and using different division ratios in the feedback path, eliminating the need for multiple separate phase interpolators and ensuring consistent performance across all phase outputs
Solution Approach 2:
The patent merges multiple independent phase interpolator functions into a single integrated phase-locked loop system. Instead of having separate phase interpolation circuits for different phase ranges, the system combines them into one unified structure where the phase detector and loop filter work together with a single oscillator to generate all required phase signals, reducing the impact of manufacturing variations
3Productivity
If the phase interpolator operates at high speed to match data transmission rates, then the productivity is improved, but the non-linearity effects become more significant, degrading data quality
Solution Approach 1:
The patent implements real-time feedback control where the phase detector continuously monitors phase errors at the high operating speed and immediately adjusts the oscillator frequency through the loop filter. This closed-loop feedback mechanism ensures that even at high data transmission speeds, phase accuracy is maintained by dynamically compensating for non-linearity effects, thus improving data quality without sacrificing productivity
Solution Approach 2:
The patent introduces dynamic adjustment capabilities to the phase interpolator system. The phase-locked loop continuously adapts the oscillator frequency and phase in real-time based on detected errors, allowing the system to maintain high-speed operation while dynamically correcting non-linearity effects. The system transitions from a static, fixed-phase approach to a dynamic, adaptive approach that can respond to and correct errors at the operating speed
Data Source
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AI summary
The present invention provides phase interpolator (200) including a phase detector (210), a filter (220) and an oscillator (230) is disclosed. The phase detector (210) is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter (220) is configured to filter the detection result to generate a filtered detection result. The oscillator (230) is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.