Sampling PLL Circuit With Detector Switching for Wide Lock Range
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in achieving fast frequency and jitter specifications required by 5G standards, particularly with narrow lock ranges and difficulties in integration due to the addition of separate frequency locking loops.
Innovation Solution
A phase-locked loop device utilizing a main loop with a voltage-controlled oscillator, divider, sampling phase frequency detector, transconductance circuit, charge pump, and loop filter, which secures a wide fixation range and proportional gain without additional loops, enabling stable phase lock and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sampling PLL is used to achieve fast frequency and jitter specifications, then frequency and jitter performance is improved, but the lock range becomes narrow making stable phase lock difficult
Solution Approach 1:
The patent implements dynamic switching between two operational modes: a first mode for fast frequency acquisition and a second mode for stable phase locking. The phase detector dynamically switches between a first phase detector for rapid frequency locking and a second phase detector for maintaining stable lock, allowing the system to adapt its characteristics based on operational requirements.
Solution Approach 2:
The patent changes key parameters dynamically by switching between different phase detectors with different characteristics. The first phase detector is optimized for fast frequency acquisition while the second is optimized for stable phase locking, allowing the system to adjust its detection parameters based on the current operational state.
2Stability of the object's composition
If a separate frequency locking loop is added to secure a fixed range, then lock range stability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the frequency locking and phase locking functions into a single integrated loop by implementing mode switching within one PLL structure. Instead of using separate frequency locking loop and phase locking loop, the system combines both functions in one loop with dynamic detector switching, reducing overall system complexity while maintaining both frequency acquisition speed and phase lock stability.
Solution Approach 2:
The single PLL loop is designed to perform multiple functions by switching between different phase detectors. The same loop structure can operate in fast frequency acquisition mode or stable phase locking mode, making the system universal and eliminating the need for separate dedicated loops for each function.
3Device complexity
If a single main loop is used without additional loops, then device complexity is reduced, but achieving wide fixation range and stable phase lock becomes difficult
Solution Approach 1:
The single main loop achieves both wide fixation range and stable phase lock through dynamic operation. The system switches between two phase detectors with different characteristics: one optimized for wide frequency acquisition range and another optimized for stable phase locking. This dynamic adaptation allows the simple single-loop structure to achieve the performance typically requiring complex multi-loop systems.
Data Source
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AI summary
A phase-locked loop device and a method for operating the same, including: a voltage-controlled oscillator configured to generate an output clock signal, a divider configured to divide the output clock signal into a first phase division signal, a sampling phase frequency detector configured to: receive a first supply voltage, a second supply voltage different from the first supply voltage, and the first phase division signal, and based on determining that a phase difference between the first phase division signal and a reference clock signal corresponds to a first interval, output a hold voltage and a status signal for the phase difference, a transconductance circuit configured to output a first conversion current based on the hold voltage, a charge pump configured to output a second conversion current based on the status signal, and a loop filter configured to provide a voltage control signal to the voltage-controlled oscillator.