Sampling PLL Reference-Voltage Circuit for Low Phase Noise
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in reducing quantization error and supply voltage fluctuations, which degrade performance and introduce phase noise, particularly in fractional-N dividers.
Innovation Solution
Implementing phase interpolation and a reference voltage generation mechanism to cancel quantization error and reduce the impact of supply voltage variations by using a delta-sigma modulator, phase detector, sampler, and a reference-voltage circuit to stabilize the control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N divider is used in the PLL to achieve frequency multiplication, then the PLL can generate a wider range of frequencies with finer resolution, but quantization error is introduced which degrades performance and increases phase noise
Solution Approach 1:
The patent converts the harmful quantization error into a useful correction signal. The quantization error detector specifically identifies the quantization error component generated by the fractional-N divider, and the quantization error DAC converts this digital error signal into an analog correction voltage that is injected back into the loop filter, thereby canceling the harmful quantization effect and improving phase noise performance
Solution Approach 2:
The patent implements a feedback mechanism where the quantization error is detected from the feedback signal, processed through the quantization error detector and DAC, and the correction voltage is fed back to the loop filter to continuously compensate for quantization errors, thereby maintaining reliable phase noise performance while using fractional-N division
2Use of energy by moving object
If the supply voltage to the PLL varies, then power consumption can be adjusted, but the control voltage becomes unstable which degrades PLL performance
Solution Approach 1:
The patent employs a counterbalancing approach by generating a reference voltage that tracks and counteracts supply voltage variations. The reference voltage generator creates a compensating signal that offsets the effect of supply voltage fluctuations on the control voltage, thereby maintaining stable PLL operation across different power consumption conditions
Solution Approach 2:
The patent changes the parameter of reference voltage to dynamically track supply voltage variations. By adjusting the reference voltage level in response to supply voltage changes, the system maintains a stable control voltage despite variations in power consumption, effectively decoupling control stability from supply voltage fluctuations
3Reliability
If quantization error correction is implemented using a capacitor-based DAC, then quantization error can be canceled, but the device complexity increases
Solution Approach 1:
The patent makes the existing feedback signal serve multiple functions: it is used both for phase detection in the conventional PLL path and for quantization error detection in the correction path. The quantization error detector extracts error information from the feedback signal without requiring a separate error detection path, and the quantization error DAC reuses the loop filter infrastructure to inject the correction voltage, thereby reducing overall device complexity
Data Source
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AI summary
In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling capacitor. The reference-voltage circuit is configured to generate a reference voltage based on a supply voltage, and generate a voltage difference between a voltage on the sampling capacitor and the reference voltage.