Sampling PLL Clock Buffer With Pulsed Switching to Cut Spur Power
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Solution Overview
Problem
Conventional sampling phase lock loops (PLLs) face issues with high power consumption and spurious output signals due to inefficient buffer circuitry and switching activity, which degrade signal-to-noise ratio and increase bit error rate.
Innovation Solution
A buffer circuit is adapted for the sampling PLL to convert a reference clock into a square wave sampling control signal, using a pulser circuit to control the switching of transistors such that they are not on simultaneously, and incorporating a delay locked loop to ensure the sampling duration is an integer multiple of the PLL output signal period, minimizing direct path current and charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional inverter buffer circuit is used to convert the reference clock to a square wave sampling control signal, then the buffer can provide the required signal conversion function, but both NMOS and PMOS transistors will be conductive simultaneously during transitions, causing direct path current to flow from VDD to GND and significantly increasing power consumption
Solution Approach 1:
The patent applies preliminary action by using a pulser circuit to preemptively control the switching of NMOS and PMOS transistors. The pulser circuit generates control signals that ensure one transistor is turned off before the other is turned on, preventing simultaneous conduction. This preliminary control action eliminates the direct path current issue before it can occur during the buffering operation.
Solution Approach 2:
The patent introduces an intermediary pulser circuit between the reference clock input and the buffer transistors. This pulser circuit acts as a mediator that processes the reference clock signal and generates appropriate control signals for the NMOS and PMOS transistors, ensuring they never conduct simultaneously. The intermediary pulser circuit thus resolves the power consumption issue without affecting the buffer's signal conversion function.
2Reliability
If the sampling switch is opened and closed in accordance with the square wave reference signal, then the sampling function is achieved, but the switching activity disturbs the VCO operation and produces spurious output signals
Solution Approach 1:
The pulser circuit serves as an intermediary that mediates between the reference signal and the sampling switch control. It shapes the control signals to ensure clean switching transitions that minimize disturbances to the VCO. The pulser circuit generates precisely timed control pulses that reduce spurious signal generation while maintaining effective sampling operation.
Solution Approach 2:
The patent applies parameter changes by modifying the timing and waveform parameters of the sampling control signals through the pulser circuit. By adjusting the pulse width, rise time, and fall time parameters of the control signals, the circuit achieves optimal switching behavior that minimizes VCO disturbance and spurious signal generation while maintaining sampling productivity.
3Reliability
If large transistor sizes are used in the inverter buffer circuit to achieve low reference clock signal noise and low PLL output jitter, then signal quality improves, but the large transistors dominate the power consumption of the overall sampling PLL circuitry
Solution Approach 1:
The pulser circuit performs preliminary control action to prevent simultaneous conduction of the buffer transistors. This allows the use of smaller transistor sizes because the direct path current issue is preemptively eliminated by the pulser's control signals, rather than relying on large transistor sizes to suppress the effect.
Solution Approach 2:
The patent applies parameter changes by modifying the transistor size parameters while compensating through pulser circuit control. The pulser circuit's precise timing control allows smaller transistors to achieve the same noise and jitter performance that would otherwise require large transistors, thus reducing power consumption while maintaining signal quality.
Data Source
AI summary
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.