SAT Solver Integrated Routing Engine for IC Design Rule Compliance
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Solution Overview
Problem
The increasing complexity of large-scale integrated circuit (IC) design poses challenges in efficiently routing metal wires, often resulting in design rule violations that require manual intervention, slowing down the process and increasing user workload.
Innovation Solution
Integration of a Boolean Satisfiability (SAT) solver with a routing engine to automatically diagnose and resolve design rule violations by using a SAT database to update routing constraints and perform Boolean constraint propagation, enabling backtracking and reordering of routing pairs to find viable paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a router is used to route metal wires in large-scale IC chips, then routing connections can be established, but design rule violations occur that require manual intervention
Solution Approach 1:
The system implements feedback by having the SAT solver continuously check routing constraints and provide information back to the router. The SAT solver evaluates whether proposed routing paths satisfy design rules and constraints, and this feedback guides the router to adjust its path selection to avoid violations, thereby maintaining high routing speed while ensuring design rule compliance.
Solution Approach 2:
The SAT solver acts as an intermediary between the router and the design rules. Instead of the router directly checking complex design rules, the SAT solver serves as a mediator that evaluates routing paths against constraints and provides guidance to the router, enabling automated resolution of design rule violations without manual intervention.
2Reliability
If manual intervention is performed to fix design rule violations, then routing compliance is improved, but the routing process slows down and user workload increases
Solution Approach 1:
The system implements self-service by enabling the router and SAT solver to automatically detect and resolve design rule violations without human intervention. The SAT solver autonomously evaluates routing paths against constraints and guides the router to select compliant paths, allowing the system to correct its own errors and maintain high compliance rates while minimizing additional routing time.
3Productivity
If the routing engine searches for paths between all pairs of points, then complete routing coverage is achieved, but the complexity of managing routing constraints increases
Solution Approach 1:
The system applies segmentation by dividing the routing problem into discrete pairs of points that need to be connected. The SAT solver evaluates constraints for each pair independently, breaking down the complex overall routing problem into manageable segments. This allows complete routing coverage to be achieved while simplifying constraint management through modular evaluation of each routing pair.
Data Source
AI summary
One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.